Versatile Video Coding (VVC), standardized in 2022 as ITU-T Recommendation H.266, ISO/IEC 23090-3 and MPEG-I Part3, is the latest block-based hybrid video coding standard. It defines many tools to increase compression efficiency while maintaining the same quality level. The tradeoff is the computational complexity. The intra-coding loop of VVC is computationally very complex due to its nature of iteratively trying all possible Quad-Tree Multitype-Tree (QTMT) partitioning alternatives starting from 128x128 Coding Tree Unit (CTU) size and going down to 4x4 min Coding Unit (CU) size. For camera-taken real-world broadcast video, compared to smaller resolutions, the objects in 8K are larger with respect to the fixed CTU size of VVC. As a result, for such 8K video, less detailed coding in the VVC QTMT may be enough for practical purposes. In this paper, we define a new fast intra-partitioning algorithm for 8K video and compare its performance with Common Test Conditions (CTC) All-Intra (AI) configuration based on the compression efficiency (bits), quality (Y-PSNR, SSIM and MS-SSIM metrics), and computational complexity (runtime). We observe 81.61% runtime gain with only 2.99% increase in bitrate, 0.1339 dB decrease in Y-PSNR, 0.0022 decrease in SSIM and 0.0007 decrease in MS-SSIM on average. This is a remarkable gain in complexity with a limited effect on efficiency and quality.

In optical communication systems, transimpedance amplifiers (TIAs) play a critical role as they are used in the front end of receivers to sense the optical inputs thereby converting them into electrical signals. In this paper, a low noise, high gain, and low power TIA is presented in 40 nm CMOS technology. To compensate for the low intrinsic gain of the technology, a structure, which comprises a shunt-shunt feedback amplifier for the first stage and two post-amplifiers for the following stages are designed. Active inductive loads are employed to extend the bandwidth. Post-layout simulation results show that the designed TIA has a bandwidth over 5 GHz, a transimpedance gain 75 dBΩ, and an input-referred noise current in bandwidth less than 8 pA/√Hz. The total layout occupies a chip estate of 0.0052 mm2while the DC power consumption is found to be 7.15 mW without the output buffer, using a single 1.1 V power supply.

Performance of analog circuits degrades over time due to several time-dependent degradation mechanisms. Due to the increased aging problems in ever-shrinking dimensions, reliability of complementary metal-oxide-semiconductor analog circuits has become a major concern. Overdesign is a popular aging-aware circuit design approach, where circuit operation is guardbanded by choosing the design point beyond the optimal region. For the sake of reliability, power consumption and chip area are sacrificed in this approach, which is undesirable considering strict energy limitations in modern applications. Conversely, Sense and React (S8R) approach serves the same purpose without any additional power consumption, in which degradation of circuit features is detected by online monitoring and recovered immediately. Furthermore, such systems enable remote control and healing of circuits. However, design of an S8R system is quite complicated. In particular, determination of efficient aging signatures and design of recovery strategy are highly challenging problems. This study thoroughly discusses the design process of S8R systems and proposes computer-aided-design-based design strategies that reduce the designer effort considerably. A novel design automation tool for S8R systems was developed, in which signature selection and recovery determination were integrated. To demonstrate proposed design strategies, two different S8R systems are implemented, simulated, and discussed in detail.

With the growing use of analog circuits in sensor systems for internet of things applications, estimation of their yield has become critical in order to increase the efficiency of large volume manufacturing. In this paper, a methodology to estimate the yield of analog circuits beyond 95% is proposed. The methodology is based on an algorithm that uses adaptive sampling to approach the “tail” region of the initial distribution which contains the dysfunctional units. These units do not satisfy the initial design targets thereby lowering the yield. An inverter and a two-stage operational amplifier have been used to verify the methodology where the reference distribution is based on 10^6 samples for both circuits. Simulation results reveal that the accuracy for 95%, 98%, and 99% yield has been compromised by less than 2.1%, 5.7%, and 7.4%, respectively, whereas the computation cost is reduced by 20x.

This study presents a parasitic-aware RF circuit synthesis tool, in which layout-induced parasitics of passive devices are captured by using sophisticated equivalent models for them. Recently, analog circuit design has been fully automated, where a circuit sizing is followed by a layout generator. However, there is often a discrepancy between synthesis and post-layout results, especially for RF applications, due to severe layout-induced parasitics of passive devices. Therefore, a number of iterations between circuit sizing and layout generator are required to achieve a fully satisfactory solution, which lead to dramatically increased synthesis times. The proposed approach provides more realistic results at the sizing part via optimizing physical parameters of passive devices, rather than their electrical values, thus, iteration count between circuit sizing and layout generation can be kept at a minimum.

This paper proposes a novel multi-objective yield aware analog sizing tool that utilizes scrambled Quasi Monte Carlo (QMC) approach for efficient yield estimation and Strength Pareto Evolutionary Algorithm-2 (SPEA2) as a search engine. Analog circuit sizing tools have been utilized for the last two decades to overcome challenging trade-offs in analog circuit design. However, due to the variation phenomenon, some solutions at the Pareto front (PF) move towards the suboptimal region. To overcome this issue, yield aware optimization tools, where yield is given as a new design objective, have been proposed in the last decade. Conventionally, Monte Carlo (MC) approach has been used for the yield estimation. However, large sized MC analysis is a highly inefficient and time consuming process because of the numerous simulations performed during the optimization process. Rather than conventional MC, using QMC, which utilizes Low Discrepancy Sequences (LDS), enhances the synthesis time since, it promises low estimation errors with fewer number of simulations. Thanks to the QMC based variability analysis and multi-objective search engine, a yield aware PF that allows the designer to access all robust solutions can be obtained within an acceptable synthesis time.

The design of complex analog circuits by using flat optimization-based approaches is inefficient, even impossible, due to the high number of design variables and the growth of the cost of performance evaluation with the circuit size. Over the past two decades, top-down hierarchical design approaches have been developed and applied. They are based on hierarchical circuit decomposition and specification transmission from top-level to lower level blocks. However, such specification transmission is usually performed with little knowledge on the feasibility of the specifications, leading, therefore, to costly redesign iterations. Even if the specification transmission is successful, there is no guarantee that it is optimal in terms of e.g., power consumption or area occupation. To palliate this problem, two novel model-based hierarchical synthesis methods are proposed in this paper: ModelBased Hierarchical Optimization (MBHO) and Improved ModelBased Hierarchical Optimization (IMBHO). They are based on the concurrent design at higher and lower hierarchical levels and appropriate communication between the different processes. Experimental results on a filter example comparing the new approaches and the conventional top-down design approach are provided.

Failure due to aging mechanisms is an important concern for RF circuits. In-field aging results in continuous degradation of circuit performances before they cause catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is not just determined by aging at the device level, but also by the slack in the specifications, process variations, and the stress conditions on each of the devices. In this paper, we present a methodology for analyzing, monitoring, and mitigating performance degradation in cross-coupled LC oscillators caused by aging mechanisms in MOSFET devices. At design time, we identify reliability hot spots and concentrate our efforts on improving these components. We aim at altering degradation patterns of important performance parameters, thereby improving the lifetime of the circuit with low area and no performance impact. We use simulations based on verified aging models to evaluate the monitoring and mitigation techniques and show that the proposed methods can increase the lifetime of the devices with no impact on the initial performance.

Finding the value and/or index of the maximum (or minimum) element of a set of$n$numbers (each with$k$-bits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximum-finder (or minimum-finder) circuit topologies, which are parallel. We wrote circuit generators at hardware description language level for our topologies and previous works. Then we synthesized these circuits for 20 different$(n, k)$cases (with values up to 64) and compared their efficiency in timing (latency), area, and energy. The timing complexity of our fastest topology is O(log$n$+ log$k$), whereas the fastest in the literature is O(log$n$log$k$). The synthesis results showed that our fastest topology is 1.2-2.2 times (1.6 times on the average) faster than the state-of-the-art. In this paper, we argue that a more fair metric of area efficiency is area-timing product. In terms of ATP, our proposed topologies are better than the state-of-the-art in 19 out of the 20 cases. In terms of energy (i.e., power-timing product, abbreviated as PTP), we are better in 11 cases out of 20.

Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (low-latency) circuits to carry out this operation. We propose a fast circuit topology called Array-Based maximum finder (AB) to determine both value and address of the maximum element within an n-element set of k-bit binary numbers. AB is based on carrying out all of the required comparisons in parallel and then simultaneously computing the address as well as the value of the maximum element. This approach ends up with only one comparator on the critical path, followed by some selection logic. The time complexity of the proposed architecture is O(log2n + log2k) whereas the area complexity is O(n2k). We developed RTL code generators for AB as well as its competitors. These generators are scalable to any value of n and k. We applied a standard-cell based iterative synthesis flow that finds the optimum time constraint through binary search. The synthesis results showed that AB is 1.2-2.1 times (1.6 times on the average) faster than the state-of-the-art.

A methodology to optimize the area of a fixed non-slicing floorplan is presented in this paper. Areas of transistors, capacitors and resistors are formulated as convex functions and area is minimized by solving a sequence of convex problems. The methodology is practical even with many components and variants. Moreover symmetry constraints are satisfied during optimization.

Ring Oscillators (RO) are the main primitives of Physical Unclonable Functions (PUFs) that generate chip specific signatures depending on the uncontrollable components present in the manufacturing process. RO-PUFs are one of the popular PUF types among various structures presented in the literature. However, due to the noisy nature of RO circuits, robust output generation is problematic in RO-PUFs. Maximizing the robustness of a PUF is the main design objective, and analytical solutions have not been developed yet to overcome this problem. In this work, RO structures are analyzed and the effects of RO inverter count and measurement time are examined theoretically and practically in terms of jitter and spatial variation. Next, a design methodology is presented to easily determine the measurement time and RO inverter count for best performing RO-PUFs. In addition to this, the design methodology is practically verified by comparing the jitter and spatial variation to the robustness measurements of previously built RO-PUF circuits.

This paper presents Fast Instruction SyntHesis (FISH), a system that supports automatic generation of custom instruction processors from high-level application descriptions to enable fast design space exploration. FISH is based on novel methods for automatically adapting the instruction set to match an application in a high-level language such as C or C++. FISH identifies custom instruction candidates using two approaches: 1) by enumerating maximal convex subgraphs of application data flow graphs and 2) by integer linear programming (ILP). The experiments, involving ten multimedia and cryptography benchmarks, show that our contributed algorithms are the fastest among the state-of-the-art techniques. In most cases, enumeration takes only milliseconds to execute. The longest enumeration run-time observed is less than six seconds. ILP is usually slower than enumeration, but provides us with a complementary solution technique. Both enumeration and ILP allow the use of multiple different merit functions in the evaluation of data-flow subgraphs. The experiments demonstrate that, using only modest additional hardware resources, up to 30-fold performance improvement can be obtained with respect to a single-issue base processor.

In this paper, we present a new layout level automation tool for analog CMOS circuits, namely, analog layout generator (ALG). ALG is capable of generating individual or matched components as well as placement and routing. ALG takes performance considerations into account, optimizing the layout in each step. A distinguishing feature of the tool is primarily providing spectra of generation possibilities ranging from full custom to automatic generation. ALG is not only designed to work as a standalone tool but also implemented to be the final step of an analog automation flow. The flow supports circuit level specification in addition to layout level user specifications, so that it can be integrated into an analog automation system. Another feature of ALG is its interaction with a layout adviser tool, namely, YASA. YASA performs sensitivity simulations using a spicelike simulator providing sensitivities of performance parameters with respect to circuit parameters.

Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and silicon area combinations. This work introduces a novel method for adapting the instruction set to match an application captured in a high-level language. A simplified model is used to find the optimal instructions via enumeration of maximal convex subgraphs of application data flow graphs (DFGs). Our experiments involving a set of multimedia and cryptography benchmarks show that an order of magnitude performance improvement can be achieved using only a limited amount of hardware resources. In most cases, our algorithm takes less than a second to execute.

This paper describes an integer-linear-programming (ILP)-based system called custom hardware instruction processor synthesis (CHIPS) that identifies custom instructions for critical code segments, given the available data bandwidth and transfer latencies between custom logic and a baseline processor with architecturally visible state registers. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions. We describe a design flow to identify promising area, performance, and code-size tradeoffs. We study the effect of input/output constraints, register-file ports, and compiler transformations such as if-conversion. Our experiments show that, in most cases, the solutions with the highest performance are identified when the input/output constraints are removed. However, input/output constraints help our algorithms identify frequently used code segments, reducing the overall area overhead. Results for 11 benchmarks covering cryptography and multimedia are shown, with speed-ups between 1.7 and 6.6 times, code-size reductions between 6% and 72%, and area costs ranging between 12 and 256 adders for maximum speed-up. Our ILP-based approach scales well: benchmarks with basic blocks consisting of more than 1000 instructions can be optimally solved, most of the time within a few seconds.

The authors present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. The authors describe a scalable integer linear programming (ILP) formulation, that extracts the most profitable set of instruction-set extensions given the available data bandwidth and transfer latency. Unlike previous approaches, the authors differentiate between number of inputs and outputs for instruction-set extensions and the number of register file ports. This differentiation makes the approach applicable to architectures that include architecturally visible state registers and dedicated data transfer channels. The authors support a comprehensive design space exploration to characterize the area/performance trade-offs for various applications. The authors evaluate our approach using actual ASIC implementations to demonstrate that our automatically customized processors meet timing within the target silicon area. For an embedded processor with only two register read ports and one register write port, the authors obtain up to 4.3times speed-up with extensions incurring only a 35% area overhead

A tool created in MATLAB environment for automatic transfer function generation and topology synthesis for a sigma delta modulator for a desired frequency response is proposed in this work. The tool carries out two basic tasks: (1) transfer function generation, which works in a SPICE like fashion, taking the netlist of an arbitrary SD modulator architecture in block level as the input, determining the input-output relation for each block in z-domain and generating the signal and noise transfer functions (STF and NTF) of the system automatically, (2) a topology synthesis algorithm which uses the STF and NTF as inputs and finds all the possible SD modulator topologies (according to some criteria such as minimization of the number of signal paths) which can be obtained from the architecture and which realizes a desired frequency response. The application of the tool will be illustrated on examples

In this paper, a tool generated in MATLAB environment for automatic modeling and architecture synthesis of sigma-delta (SD) modulators is described. The tool is capable of generating the parametric signal and noise transfer functions (STF and NTF) of an SD modulator of any order. After generating the transfer functions, it optimizes both the STF and the NTF of the system simultaneously in such a way to realize a desired frequency response. Most important of all, this tool is capable of taking component non-idealities into account and optimizing the coefficients so as to compensate the effects of non-idealities on the system. Integrator non-idealities (the switched capacitor mismatches and integrator leakage due to finite DC gain of the op-amp, etc.) are given as examples in the paper. The tool uses some criteria such as minimization of the number of signal paths of the architecture in order to obtain minimum possible complexity and avoiding of single closed loops without a delay. Also, another important aspect of the tool is that it spans the whole solution space according to this criterion and returns a set of several parametric solutions.

As RF IC design has become more prevalent and more demanding, the need for a more precise VCO phase noise model has arisen. For both MOS and bipolar VCO's new formulas are still being proposed to model the phase noise, which is a key factor for a precise oscillator. In this paper, a previous phase noise model for a bipolar VCO as presented in A. Tasic and W. A. Serdijn (2002) is refuted and the formulas developed for MOS VCO phase noise calculations based in J. J. Rael and A. Abidi (2000) are adapted to bipolar VCO. Then, the results are compared and some conclusions are drawn for the comparison of these oscillators.

This paper presents an analog integrated circuit synthesis system based on an evolutionary approach. The system contains several novel features. One of these is the high-performance optimization algorithm, which is a combination of evolutionary strategies and simulated annealing. Modeling of dc parameters is done via a fast dc simulator developed for this purpose whereas modeling of ac parameters can be done either with user-defined equations or with neural-fuzzy performance models trained from SPICE simulations. Another novel feature of the system is the incorporation of matching properties of devices. This way, the optimized circuit becomes tolerant to process variations. The synthesis system has been tested on several independent examples and synthesized circuits have been verified functionally with SPICE simulations. Finally, a prototype chip composed of the three examples has been manufactured. The measurement results have demonstrated the validity of the synthesis system on silicon.

In this paper, an evolution-based approach to design of neural fuzzy networks is presented. The proposed strategy optimizes the whole fuzzy system with minimum rule number according to given specifications, while training the network parameters. The approach relies on an optimization tool, which combines evolution strategies and simulated annealing algorithms in finding the global optimum solution. The optimization variables include membership function parameters and rule numbers which are combined with genetic parameters to create diversity in the search space due to self-adaptation. The optimization technique is independent of the topology under consideration and capable of handling any type of membership function. The algorithmic details of the optimization methodology are discussed in detail, and the generality of the approach is illustrated by different examples.

A GRBF network is designed for VLSI implementation. Building blocks of the network consist mainly of analog circuits: op amp, multiplier, multiplying DAC (digital to analog converter), floating resistor, summer and exponentiator. Parameters of the network (center, width of the Gaussian function and output layer weights) are represented digitally for convenient interfacing. It is shown that individual GRBF units allow independent tuning of center, width and amplitude. Several network structures are simulated as function approximation examples, and the performance is verified to be satisfactory.

The commenters point out and correct the errors in the derivations of the equations appeared in the above paper by Dundar and Rose (ibid., vol.6 (1995)). In reply, Dundar and Rose agree with their corrections and state that the errors are relatively small and should not affect the conclusions.

The problems arising from the use of nonlinear multipliers in multilayer neural network synapse structures are discussed. The errors arising from the neglect of nonlinearities are shown and the effect of training in eliminating these errors is discussed. A method for predicting the final errors resulting from nonlinearities is described. Our approximate results are compared with the results from circuit simulations of an actual multiplier circuit.

The effect of weight quantization in multilayer neural networks is discussed. A method is derived by which one can predict the performance degradation at the output given the properties of the network and number of bits of quantization. Predictions from this method are evaluated against simulation results. An algorithm to decrease the noise at the output is presented and the results are compared with those above.