A novel machine learning modeling methodology for parasitic capacitance extraction of middle-end-of-line metal layers around FinFETs and MOSFETs is developed. Due to the increasing complexity and parasitic extraction accuracy requirements of middle-end-of-line patterns in advanced process nodes, most of the current parasitic extraction tools rely on field-solvers to extract middle-end-of-line parasitic capacitances. As a result, a lot of time, memory, and computational resources are consumed. The proposed modeling methodology overcomes these problems by providing compact models that predict middle-end-of-line parasitic capacitances efficiently. The compact models are pre-characterized and technology-dependent. Also, they can handle the increasing accuracy requirements in advanced process nodes. The proposed methodology scans layouts for devices, extracts geometrical features of each device using a novel geometry-based pattern representation, and uses the extracted features as inputs to the required machine learning models. Two machine learning methods are used including: support vector regressions and neural networks. The testing covered more than 40M devices in several different real designs that belong to 28nm and 7nm process technology nodes. The proposed methodology managed to provide outstanding results as compared to field-solvers with an average error < 0.2%, a standard deviation < 3%, and a speed up of 100X.

As process technologies scale down, the accuracy requirements of parasitic capacitance extractions for integrated circuits significantly increase. This work introduces a novel accuracy-based hybrid parasitic capacitance extraction flow, where the chip is subdivided into windows, and each window’s capacitances are calculated using one of three extraction methods: field-solver, rule-based, and novel deep-neural-networks-based methods. This hybrid methodology uses a density-map feature representation as an input to neural-networks classifiers to determine an extraction method for each window. As an intermediate method between rule-based and field-solver methods, a novel deep-neural-networks-based extraction method is introduced. This intermediate level of accuracy and speed is needed since using only rule-based and field-solver methods results in using the field-solver most of the time for any required high accuracy extraction. This method uses a novel hybrid density-voltage representation as an input to improve its accuracy and speed. The proposed hybrid flow identifies the accuracy limits of the three extraction methods and directs each window to the fastest method that meets the user predetermined accuracy level. The proposed flow is tested on different real designs and showed outstanding accuracy and runtime as compared to commercial field-solver and rule-based tools. The results show that the proposed deep-neural-networks extraction method extracts capacitances of complicated structures with high accuracy ($100\times $faster than field-solvers. However, few outliers have an error exceeding 5% in extracted capacitances. Furthermore, the proposed hybrid flow managed to meet the required accuracy ($70\times $faster than field-solvers.

Presented in this paper is a tool that automatically migrates analog designs from one process to another while keeping circuit and layout topologies. A netlist migration engine recalculates the new device dimensions in the target technology followed by a layout migration engine that compacts the design according to the new process design rules. The overall framework preserves design intelligence embedded in the original IP such as symmetry, hierarchy, placement and routing. The circuit migration engine, being very fast, can retarget large analog blocks in only a few minutes while giving same or better performance of the original design. The migration of 3 different circuits is presented to validate the overall methodology. These circuits have been fabricated and measured.