Wearable and implantable technology for respiratory monitoring has created the potential for continuous collection of respiratory parameters for healthcare and other applications. However, battery life, form factor, and user burden impose practical constraints that affect user acceptance and therefore clinical utility. This work introduces a wireless self-powered sensing system for airway monitoring that uses an array of piezoelectric cantilevers that functions as both the respiratory flow sensor and the energy harvester that powers the system. The cantilevers are excited by airflow in the airway, and the harvested energy from the cantilevers is stored in a capacitor. Once a threshold energy is available in the capacitor, a load switch closes and enables a low frequency oscillator that functions as a data-less transmitter. The signal coming from the sensing system is received by an external software-defined radio (SDR), and the rate at which this signal is received is mapped to the respiratory conditions in the airway. A benchtop testing system that incorporates a lung simulator, a data acquisition system, and a hot wire anemometer was created to validate the sensor. Results show that the signal reception rate is affected by the breathing rate and volume, demonstrating the potential for a self-powered, miniaturized, passive implantable device for continuous respiratory health monitoring.

While relying on energy harvesting to power Internet of Things (IoT) devices eliminates the maintenance burden of battery replacement, energy generation fluctuation constitutes a major source of uncertainty to design reliable self-powered IoT devices. To characterize spatial-temporal variability of energy harvesting, data acquisition campaigns are needed across the range of potential harvesting sources. In this work we present a dataset to characterize thermal energy sources in residential settings by measuring thermoelectric generator (TEG) operating conditions over 16 deployment locations for periods ranging from 19 to 53 days. We present our easy-to-use thermal energy measurement platform built from off-the-shelf component modules and a custom TEG interface circuit. We demonstrate how the collected measurements can inform the design of energy harvesting IoT devices by deriving the TEG's maximum power output and estimating the available energy at each harvesting location.

Modern processors often need to switch among different power states based on usage scenarios, energy availability, and thermal conditions. Dynamic voltage and frequency scaling (DVFS) is a commonly used power management strategy to trade off performance and energy. As transistor scaling is reaching its limit, the viable supply voltage range where DVFS can operate is shrinking, which limits its effectiveness. To extend the performance-energy trade-off capabilities in modern processors, this article proposes dynamic core scaling (DCS) that does not rely on voltage scaling. DCS dynamically adjusts the active superscalar datapath resources so that programs run at a given percentage of their maximum speed while minimizing energy consumption at the same time. Since DCS does not need voltage scaling, it can be combined with DVFS to achieve greater energy savings. To effectively manage performance-energy trade-offs using a combination of DCS and DVFS, this article proposes an oracle controller that demonstrates the optimal control strategy, and two practical controllers that are applicable in real implementations. Evaluations using an 8-way superscalar processor implemented in a 45-nm circuit show that DCS is more effective in performance-energy trade-offs than DVFS at the high performance end for a number of SPEC CPU2000 benchmarks. When used together with DVFS, DCS saves an additional 20 percent of a full-size core’s energy on average. At the minimum operating voltage, DVFS hits its limit, while DCS is still able to achieve an average of 46 percent further energy reduction.

Continuous monitoring of breathing rate (BR), minute ventilation (VE), and other respiratory parameters could transform care for and empower patients with chronic cardio-pulmonary conditions, such as asthma. However, the clinical standard for measuring respiration, namely Spirometry, is hardly suitable for continuous use. Wearables can track many physiological signals, like ECG and motion, yet respiration tracking faces many challenges. In this work, we infer respiratory parameters from wearable ECG and wrist motion signals. We propose a modular and generalizable classification-regression pipeline to utilize available context information, such as physical activity, in learning context-conditioned inference models. Novel morphological and power domain features from the wearable ECG are extracted to use with these models. Exploratory feature selection methods are incorporated in this pipeline to discover application-driven interpretable biomarkers. Using data from 15 subjects, we evaluate two implementations of the proposed inference pipeline: for BR and VE. Each implementation compares generalized linear model, random forest, support vector machine, Gaussian process regression, and neighborhood component analysis as regression models. Permutation, regularization, and relevance determination methods are used to rank the ECG features to identify robust ECG biomarkers across models and activities. This work demonstrates the potential of wearable sensors not only in continuous monitoring, but also in designing biomarker-driven preventive measures.

With the advancement of wearable sensor technology, the use of inertial body sensors in the field of Medicine and Healthcare has increased drastically. Researchers have found that gait data is useful for identifying various motion impairments. Current research in gait analysis is incorporating the features extracted from video data, which is hard to analyze and requires expensive video capture equipment to collect data in slow motion. In this study, we utilized the ability of inertial body sensors to capture gait features of individuals with Anterior Cruciate Ligament (ACL) injury. This study also leverages the causality-based approach to find the coordination between different features of gait data. Gait data during walking, jogging, and running was collected from 131 subjects in which 109 have ACL injury. We then utilized this data to incorporate the gait assessment technique, which uses causality analysis to predict various classes of subjects based on health condition, impacted limb, and impacted limb based on gender. Performance metrics of various machine learning (ML) algorithms were compared to observe the best performing algorithm and used it to evaluate the confidence of individual subjects prediction that aids personalized classification.

While body sensor networks (BSNs) have proven to be a feasible solution for long-term vigilant health monitoring, limited battery life remains one of the main factors that has impeded their widespread adoption. Energy harvesting technologies bring an opportunity to address this issue by enabling the development of self-powered BSNs. However, the dynamic nature of energy harvesting sources poses a challenge to self-powered vigilance. In this paper, an application-driven dynamic power management (DPM) method for self-powered BSNs is presented that optimally adapts system operation to energy availability while meeting application requirements for vigilant monitoring. Vigilant Atrial Fibrillation (AF) monitoring is investigated as an example case study, and a simulation using real-world energy harvesting profiles is executed to validate the model and the optimal solution.

Gait impairment in multiple sclerosis (MS) can result from muscle weakness, physical fatigue, lack of coordination, and other symptoms. Walking speed, as measured by a number of clinician-administered walking tests, is the primary measure of gait impairment used by clinical researchers, but inertial gait features from body-worn sensors have been proven to add clinical value. This paper seeks to understand and differentiate the physiological significance of four such features with proven value in MS to facilitate adoption by clinical researchers and incorporation in gait monitoring and analysis systems. In addition, this information can be used to select features that might be appropriate in other forms of disability. Two of the four features are computed using the dynamic time warping (DTW) algorithm: The "DTW Score" is based on the usual DTW distance, and the "Warp Score" is based on the warping length. The third feature, based on kernel density estimation (KDE), is the "KDE Peak" value. Finally, the "Causality Index" is based on the phase slope index between inertial signals from different body parts. Relationships between these measures and the aforementioned gait-related symptoms are determined by applying factor analysis to three common, clinical walking outcomes, then correlating the inertial measures as well as walking speed to each extracted factor. Statistically significant differences in correlation coefficients to the three extracted clinical factors support their distinct physiological meaning and suggest they may have complimentary roles in the analysis of MS-related walking disability.

Energy harvesting is a promising solution to the limited battery lifetimes of body sensor nodes. Self-powered sensor systems capable of quasi-perpetual operation enable the possibility of truly continuous monitoring of patients beyond the clinic. However, the discontinuous and dynamic characteristics of harvesting in real-world scenarios-and their implications for the design and operation of self-powered systems-are not yet well understood. This paper presents a mobile energy harvesting and data collection (EHDC) platform designed to provide a deeper understanding of energy harvesting dynamics. The EHDC platform monitors and records the instantaneous usable power generated by body-worn harvesters, while also collecting human activity and environmental data to provide a comprehensive real-world evaluation of two energy harvesting modalities common to body sensor networks: solar and thermoelectric. The platform was initially validated with benchtop tests and later with real-world deployments on two subjects. 7-h-long multimodal energy harvesting profiles were generated, and the environmental and behavioral data were used to expand upon previously developed Kalman filter based mathematical models for energy harvesting prediction. Results confirm the validity of the EHDC platform and harvesting models, establishing the potential for longer term monitoring of energy harvesting characteristics; thus, informing the design and operation of self-powered body sensor networks.

Nowadays, a large amount of services are deployed on the edge of the network from the cloud since processing data at the edge can reduce response time and lower bandwidth cost for applications such as healthcare in smart homes. Resource management is very important in the edge computing since it is able to increase the system efficiency and improve the quality of service. A common approach for resource management in edge computing is to assign tasks to the remote cloud or edge devices just according to several factors such as energy, bandwidth consumption, and latency. However, the approach is insufficiently efficient and falls short in meeting the requirements of handling health emergency when being applied in smart homes for healthcare. In this paper, we propose a task scheduling approach called HealthEdge that sets different processing priorities for different tasks based on the collected data on human health status and determines whether a task should run in a local device or a remote cloud in order to reduce its total processing time as much as possible. Based on a real trace from five patients, we conduct a trace-driven experiment to evaluate the performance of HealthEdge in comparison with other methods. The results show that HealthEdge can optimally assign tasks between the network edge and cloud, which can reduce the task processing time, reduce bandwidth consumption and increase local edge workstation utilization.

Research in the area of internet-of-things, cyberphysical-systems, and smart health often employ sensor systems at residences for continuous monitoring. Such research-oriented residential monitoring systems (RRMSs) usually face two major challenges, long-term reliable operation management and validation of system functionality with minimal human effort. Targeting these two challenges, this paper describes a monitor of monitoring systems with ground-truth validation capabilities, M2G. It consists of two subsystems, the Monitor2system and the Ground-truth validation system. The Monitor2system encapsulates a flexible set of general-purpose components to monitor the operation and connectivity of heterogeneous sensor devices (e.g. smart watches, smart phones, microphones, beacons, etc.), a local base-station, as well as a cloud server. It provides a user-friendly interface and supports different types of RRMSs in various contexts. The system also features a ground truth validation system to support obtaining ground truth in the field. Additionally, customized alerts can be sent to remote administrators and other personnel to report any dysfunction or inaccuracy of the system in real time. M2G is applied to three very different case studies: the M2FED system which monitors family eating dynamics [1], an in-home wireless sensing system for monitoring nighttime agitation [2], and the BESI system which monitors behavioral and environmental parameters to predict health events and to provide interventions [3]. The results indicate that M2G is a comprehensive system that (i) requires small cost in time and effort to adapt to an existing RRMS, (ii) provides reliable data collection and reduction in data loss by detecting faults in real-time, and (iii) provides a convenient and timely ground truth validation facility.

Nowadays, a large amount of services are deployed on the edge of the network from the cloud since processing data at the edge can reduce response time and lower bandwidth cost for applications such as healthcare in smart homes. Resource management is very important in the edge computing since it is able to increase the system efficiency and improve the quality of service. A common approach for resource management in edge computing is to assign tasks to the remote cloud or edge devices just according to several factors such as energy, bandwidth consumption, and latency. However, the approach is insufficiently efficient and falls short in meeting the requirements of handling health emergency when being applied in smart homes for healthcare. Possible health emergency needs immediate attention and different health tasks have different priorities to be processed. In this paper, we propose a task scheduling approach called HealthEdge that sets different processing priorities for different tasks based on the collected data on human health status and determines whether a task should run in a local device or a remote cloud in order to reduce its total processing time as much as possible. Based on a real trace from five patients, we conduct a trace-driven experiment to evaluate the performance of HealthEdge in comparison with other methods. The results show that HealthEdge can optimally assign tasks between the network edge and cloud, which can reduce the task processing time, reduce bandwidth consumption and increase local edge workstation utilization.

Gait impairment in Multiple Sclerosis (MS) can result from imbalance, physical fatigue, weakness, and other symptoms. Walking speed is the primary measure of gait impairment used by clinical researchers, but inertial gait features from body-worn sensors have been proven to add clinical value. This paper seeks to understand the physiologic significance of two such features in MS. Both features are computed using the dynamic time warping (DTW) algorithm: the “DTW Score” is based on the usual DTW distance, and the “Warp Score” is based on the warping length. Using linear regression and stepwise regression models, the relationship between these features and several gait-related MS symptoms is analyzed. Results show that the DTW Score and Warp Score have distinct physiologic significance in MS compared to walking speed, and these features may also be useful for walking assessment in a wide range of clinical contexts.

Energy harvesting offers the promise of mobile sensor systems capable of quasi-perpetual operation, but the discontinuous and dynamic characteristics of harvesting in real-world scenarios - necessary for the design and operation of self-powered systems - are not yet well understood. The paper presents a hardware platform for providing a comprehensive real-world evaluation of two energy harvesting modalities common to body sensor networks: indoor light and thermoelectric. Day-long multi-modal energy harvesting profiles were generated, which were then used to develop a mathematical model to predict real time energy harvesting values from the sampled environmental and human behavioral parameters. Experimental results demonstrate that the model is effective in calculating and predicting harvested energy in real time, and a multi-source scheme for continuous operation of self-powered sensors is demonstrated.

Step-by-step determination of gait parameters provides insight into the variability of specific gait patterns associated with frequent injuries in the lower extremities of adolescents and with geriatric syndromes of the elderly. Numerous methods have been developed for the step-by-step estimation of gait parameters, but most are expensive, obtrusive, inconvenient, and/or inaccurate. In this paper, we developed an innovative shoe, called the “Gait Tracker”, with a low power inertial measurement unit (IMU) embedded in a 3D printed sole that provides unobtrusive, continuous, and accurate step-by-step measurement of gait parameters for individual use. This shoe enables out-of-lab gait monitoring in a wide range of activities and over an extended period of time. Experimental results from controlled studies demonstrated that the Gait Tracker can recognize various gait events and provide better accuracy in stride length measurement compared to previous systems and methods.

The obesity epidemic is the primary cause of recent increases in heart disease, diabetes, cancer, and other diseases that place an untenable strain on healthcare and public health. One of the primary behavioral causes, i.e. dietary intake, is a behavior that science has had little success in understanding, much less affecting. Current behavioral science suggests that family eating dynamics (FED) have high potential to impact child and parent dietary intake and obesity rates. In contrast to traditional obesity related approaches that focus on dietary intakes (e.g., what and how much is being eaten), FED based approaches focus on family mealtime and home food environment (e.g., who is eating, when, where, with whom, interpersonal stress) for modeling behavior and providing feedback that has potential for successful behavior modification. This poster briefly presents M2FED, an integrated system for monitoring and modeling FED. The system is under development, and it consists of in-situ and wearable sensors, and smartphones that collect synchronized real-time FED data used to iteratively develop dynamic, contextualized FED models.

Human motion has been reported as having great relevance to various disease, disorder, injuries and emotional state. Therefore, motion assessment using inertial body sensor networks (BSNs) is gaining popularity as an outcome measure in clinical study and neuroscience research. The efficacy of motion assessment heavily relies on the accurate temporal clustering of human motion into actions on various time scales. However, two human factors in real-world deployments of inertial BSNs make such motion assessment challenging: mounting errors (where sensor displacement and orientation do not match what is assumed by processing algorithms) and insecure mounting (where sensors are loosely worn causing them to shake during operations). In order to enhance the robustness of human actions clustering from real-world BSN data, this work leverages dynamical systems modeling with the considerations of human factors. By proposing a computational body-model framework called the piecewise linear dynamical model (PLDM), we derive a robust method to segment time series data of inertial BSNs in real-world deployment with human factors into motion primitives and actions. We test the proposed method on three different inertial BSN datasets, extract actions on different temporal scales and recognize the actions into clusters. The experimental results demonstrate the effectiveness of our approach.

After decades of evolution, measuring instruments for quantitative gait analysis have become an important clinical tool for assessing pathologies manifested by gait abnormalities. However, such instruments tend to be expensive and require expert operation and maintenance besides their high cost, thus limiting them to only a small number of specialized centers. Consequently, gait analysis in most clinics today still relies on observation-based assessment. Recent advances in wearable sensors, especially inertial body sensors, have opened up a promising future for gait analysis. Not only can these sensors be more easily adopted in clinical diagnosis and treatment procedures than their current counterparts, but they can also monitor gait continuously outside clinics - hence providing seamless patient analysis from clinics to free-living environments. The purpose of this paper is to provide a systematic review of current techniques for quantitative gait analysis and to propose key metrics for evaluating both existing and emerging methods for qualifying the gait features extracted from wearable sensors. It aims to highlight key advances in this rapidly evolving research field and outline potential future directions for both research and clinical applications.

Inertial body sensors have emerged in recent years as an effective tool for evaluating mobility impairment resulting from various diseases, disorders, and injuries. For example, body sensors have been used in 6-min walk (6 MW) tests for multiple sclerosis (MS) patients to identify gait features useful in the study, diagnosis, and tracking of the disease. However, most studies to date have focused on features localized to the lower or upper extremities and do not provide a holistic assessment of mobility. This paper presents a causality analysis method focused on the coordination between extremities to identify subtle whole-body mobility impairment that may aid disease diagnosis. This method was developed for and utilized in an MS pilot study with 41 subjects (28 persons with MS (PwMS) and 13 healthy controls) performing 6 MW tests. Compared with existing methods, the causality analysis provided better discrimination between healthy controls and PwMS and a deeper understanding of MS disease impact on mobility.

Gait assessment is a common method for diagnosing various diseases, disorders, and injuries, studying their impact on mobility, and evaluating the efficacy of various therapeutic interventions. The recent emergence of inertial body sensors for gait assessment addresses the limitations of visual observation and subjective clinical evaluation by providing more precise and objective measures. Inertial sensors have been included in an ongoing study at the University of Virginia Medical Center on Multiple Sclerosis (MS), a chronic autoimmune disorder of the central nervous system (CNS) that produces neurologic impairment and functional disability over time, with the goal of improving the ability to assess MS-affected gait and to distinguish between subjects with MS and those without MS. This work presents a gait assessment technique based on causal modeling to distinguish MS-affected gait and healthy gait. The approach in this work is based on the hypothesis that the strength of interaction between body parts during walking is greater in healthy controls that in MS subjects. The strength of interaction was quantified using a causality index based on the pairwise causal relationships between body parts as characterized by the Phase Slope Index (PSI) of inertial signals from pairs of body parts. In a pilot study with 41 subjects (28 MS subjects and 13 healthy controls), the approach developed in this paper provided better separability (p <; 0.0001) compared with existing methods.

Health care continues to be one of the biggest challenges facing our society. Factors such as lifestyle choices, genetics, aging, stress and environmental exposures play a critical role in determining health outcomes. Wearable technologies that can enable continuous/long-term personal health monitoring and personal environmental monitoring can empower users to make better lifestyle decisions and improve health outcomes. While wearable devices promise a compelling future of achieving wellness, current wearable products are not addressing the needs of the health space. To achieve this future, key challenges in wearable systems such as battery life, form factor, sensor functionality, configurability and data analysis will have to be carefully addressed to ensure user adoption and effectively manage health.

Dynamic voltage and frequency scaling (DVFS) is commonly employed on modern superscalar processors to reduce energy when peak performance is not needed or allowed. As technology scales, the effectiveness of DVFS is limited by the shrinking viable supply voltage range. This work proposes dynamic core scaling (DCS) to extend performance-energy tradeoff capabilities in superscalar processors. DCS ensures that programs run at a given percentage of their maximum speed and, at the same time, minimizes energy consumption by dynamically adjusting the active superscalar datapath resources. Evaluations using an 8-way superscalar processor implemented on 45nm circuit infrastructure show that DCS is more effective in performance-energy tradeoffs than DVFS at the high performance end. When used together with DVFS, DCS saves an additional 20% of a full-size core's energy on average. At the minimum operating voltage, DVFS stops reducing energy, while DCS is still able to achieve an average of 46% further energy reduction.

To minimize the access latency of set-associative caches, the data in all ways are read out in parallel with the tag lookup. However, this is energy inefficient, as only the data from the matching way is used and the others are discarded. This paper proposes an early tag lookup (ETL) technique for L1 instruction caches that determines the matching way one cycle earlier than the cache access, so that only the matching data way need be accessed. ETL incurs no performance penalty and insignificant hardware overhead. Evaluation on a 4-way set-associative L1 instruction cache in 45nm technology shows that ETL reduces the read energy by 68% on average.

This article provides the latest advances from the NSF Advanced Self-powered Systems of Integrated sensors and Technologies (ASSIST) center. The work in the center addresses the key challenges in wearable health and environmental systems by exploring technologies that enable ultra-long battery lifetime, user comfort and wearability, robust medically validated sensor data with value added from multimodal sensing, and access to open architecture data streams. The vison of the ASSIST center is to use nanotechnology to build miniature, self-powered, wearable, and wireless sensing devices that can enable monitoring of personal health and personal environmental exposure and enable correlation of multimodal sensors. These devices can empower patients and doctors to transition from managing illness to managing wellness and create a paradigm shift in improving healthcare outcomes. This article presents the latest advances in high-efficiency nanostructured energy harvesters and storage capacitors, new sensing modalities that consume less power, low power computation, and communication strategies, and novel flexible materials that provide form, function, and comfort. These technologies span a spatial scale ranging from underlying materials at the nanoscale to body worn structures, and the challenge is to integrate them into a unified device designed to revolutionize wearable health applications.

Massively parallel computation in GPUs significantly boosts performance of compute-intensive applications but creates power and thermal issues that limit further performance scaling. This paper demonstrates significant GPGPU power savings by relaxing application accuracy requirements and enabling the use of low power imprecise hardware (IHW). A synthesized set of novel imprecise floating point arithmetic units is presented. GPGPU-Sim and GPUWattch are used to estimate impacts of IHW units on output quality and system-level power consumption, providing a quality-power tradeoff model for application-specific optimization. Experimental results for a 45 nm process show up to 32% power savings with negligible impacts on output quality.

Dynamically reconfigurable SIMD/MIMD architectures made from simple cores have emerged to exploit diverse forms of parallelism in applications [1,2]. In this work, we investigate the circuit-level overhead and flexibility tradeoffs of such architectures through the design of a custom reconfigurable SIMD/MIMD system.

Floating point multiplication is one of the most frequently used arithmetic operations in a wide variety of applications, but the high power consumption of the IEEE-754 standard floating point multiplier prohibits its implementation in many low power systems, such as wireless sensors and other battery-powered embedded systems, and limits performance scaling in high performance systems, such as CPUs and GPGPUs for scientific computation. This paper presents a low-power accuracy-configurable floating point multiplier based on Mitchell's Algorithm. Post-layout SPICE simulations in a 45nm process show same-delay power reductions up to 26X for single precision and 49X for double precision compared to their IEEE-754 counterparts. Functional simulations on six CPU and GPU benchmarks show significantly better power reduction vs. quality degradation trade-offs than existing bit truncation schemes.

To achieve high performance, conventional superscalar processors maintain maximum front-end instruction delivery bandwidth, which is often suboptimal when program behavior and priority metrics change. This paper proposes an adaptive front-end throttling technique that dynamically adjusts the front-end instruction delivery bandwidth as program behavior changes to optimize a target metric, being performance, energy, or an arbitrary trade-off between them. Circuit-level synthesis (45nm FreePDK) and simulation show that adaptive front-end throttling incurs negligible overhead but achieves average improvements of 7%, 28%, 28%, and 32% for performance, energy, energy-delay product, and energy-delay-squared product, respectively, over all benchmarks on an 8-way superscalar processor.

Body sensor networks (BSNs) have provided the opportunity to monitor energy expenditure (EE) in daily life and with that information help reduce sedentary behavior and ultimately improve human health. Current approaches for EE estimation using BSNs require tedious annotation of activity types and multiple body sensor nodes during data collection and high accuracy activity classifiers during post processing. These drawbacks impede deploying this technology in daily life — the primary motivation of using BSNs to monitor EE. With the goal of achieving the highest EE estimation accuracy with the least invasiveness and data collection effort, this paper presents an unsupervised, single-node solution for data collection and activity clustering. Motivated by a previous finding that clusters of similar activities tend to have similar regression models for estimating EE, we apply unsupervised clustering to implicitly group activities with homogeneous features and generate specific regression models for each activity cluster without requiring manual annotation. The framework therefore does not require specific activity classification, hence eliminating activity type labels. With leave-one-subject-out cross-validation across 10 subjects, an RMSE of 0.96 kcal/min was achieved, which is comparable to the activity-specific model and improves upon a single regression model.

Recent imprecise hardware (IHW) design methodologies present opportunities for achieving gains in nonfunctional efficiency design metrics by allowing errors in computation within error tolerant application domains. This work presents a novel imprecise Error Tolerant Balancing Adder (ETBA) design - an augmentation of the ETAIIM IHW adder that reduces errors by introducing a balance block that detects and corrects carry chain inconsistencies in the ETAIIM but operates off the critical path. Furthermore, this work identifies a common class of killer inputs with high error rates for IHW adders, and demonstrates the ETBA's resilience to these errors. A JPEG decompression case study reveals a 24% reduction in ETBA addition energy-delay product compared to a Kogge-Stone adder with only a 0.2% reduction in SSIM image quality.

Modeling and simulation play important roles in engineering research and design. These techniques are especially helpful in the early phases where limited detail is available about the design and where design changes are less costly. In addition, high-fidelity models can be employed at the later stages to complement testing. Models are also important research tools for understanding complex phenomena.

No abstract available.

Recent studies have demonstrated the potential for reducing energy consumption in integrated circuits by allowing errors during computation. While most proposed techniques for achieving this rely on voltage overscaling (VOS), this paper shows that Imprecise Hardware (IHW) with design-time structural parameters can achieve orthogonal energy-quality tradeoffs. Two IHW adders are improved and two IHW multipliers are introduced in this paper. In addition, a simulation-free error estimation technique is proposed to rapidly and accurately estimate the impact of IHW on output quality. Finally, a quality-aware energy minimization methodology is presented. To validate this methodology, experiments are conducted on two computational kernels: DOT-PRODUCT and L2-NORM -- used in three applications -- Leukocyte Tracker, SVM classification and K-means clustering. Results show that the Hellinger distance between estimated and simulated error distribution is within 0.05 and that the methodology enables designers to explore energy-quality tradeoffs with significant reduction in simulation complexity.

This paper explores the benefits of splitting a monolithic power gate transistor into parallel, independently controlled, variable weighted power gates to provide programmable post-fabrication power grid resistance. This power gate topology creates energy saving opportunities by providing adjustable localized voltages during active modes and reducing leakage current in idle blocks while retaining data. Measurements show over 30% active energy savings per operation and 90% savings in idle current with retention. A modeling flow for a resistive power grid was also developed that demonstrates the effectiveness of this approach in a Bulldozer processor core.

This paper presents a charge-pump based low swing interconnect receiver circuit. The interconnect circuit is single ended and supports swings of 300mV or lower. A charge pump front end at the receiver boosts the arriving signal before restoring it to the full logic level, improving the performance of the interconnect. For a 10mm long interconnect wire in a 45nm CMOS process, the proposed scheme provides 3X energy reduction at constant speed and 3.5X delay improvement at constant energy relative to prior art. We deploy the interconnect scheme as the data bus between the L1-L2 caches of a 4-core Alpha processor. Over a set of Splash benchmarks, the proposed architecture reduces total energy consumption by 70% while maintaining the same performance.

Body sensor networks (BSNs) are emerging cyber–physical systems that promise to improve quality of life through improved healthcare, augmented sensing and actuation for the disabled, independent living for the elderly, and reduced healthcare costs. However, the physical nature of BSNs introduces new challenges. The human body is a highly dynamic physical environment that creates constantly changing demands on sensing, actuation, and quality of service (QoS). Movement between indoor and outdoor environments and physical movements constantly change the wireless channel characteristics. These dynamic application contexts can also have a dramatic impact on data and resource prioritization. Thus, BSNs must simultaneously deal with rapid changes to both top–down application requirements and bottom–up resource availability. This is made all the more challenging by the wearable nature of BSN devices, which necessitates a vanishingly small size and, therefore, extremely limited hardware resources and power budget. Current research is being performed to develop new principles and techniques for adaptive operation in highly dynamic physical environments, using miniaturized, energy-constrained devices. This paper describes a holistic cross-layer approach that addresses all aspects of the system, from low-level hardware design to higher level communication and data fusion algorithms, to top-level applications.

Energy-fidelity trade-offs are central to the performance of many technologies, but they are essential in wireless body area sensor networks (BASNs) due to severe energy and processing constraints and the critical nature of certain healthcare applications. On-node signal processing and compression techniques can save energy by greatly reducing the amount of data transmitted over the wireless channel, but lossy techniques, capable of high compression ratios, can incur a reduction in application fidelity. In order to maximize system performance, these trade-offs must be considered at runtime due to the dynamic nature of BASN applications, including sensed data, operating environments, user actuation, etc. BASNs therefore require energy-fidelity scalability, so automated and user-initiated trade-offs can be made dynamically. This article presents a data rate scalability framework within a motion-based health application context which demonstrates the design of efficient and efficacious wireless health systems.

Recently many imprecise circuit design techniques have been proposed for implementation of error-tolerant applications, such as multimedia and communications. These algorithms do not mandate absolute correctness of their results, and imprecise circuit components can therefore leverage this relaxed fidelity requirement to provide performance and energy benefits. In this paper, several imprecise adder design techniques are classified and compared in terms of their error characteristics and power-delay efficiency. A general methodology for fidelity-efficiency design space exploration is presented and is applied to a case study implementing the CORDIC algorithm in 130nm technology. The case study reveals that simple precision scaling often provides better power-delay efficiency for a given fidelity than more complex imprecise adders, but different choice of algorithm and fidelity can influence the outcome.

The fidelity of many inertial Body Sensor Network (BSN) applications depends on accurate spatio-temporal information retrieved from body-worn devices. However, there are many challenges caused by inherent sensor errors in inertial BSNs and the uncertainty of dynamic human motion in various situations, such as integration drift and mounting error. Spatial information is especially difficult to extract from inertial data. This paper presents practical methods to minimize errors caused by these challenges within the context of a case study -- gait speed estimation - where both temporal and spatial information are crucial for accuracy. These methods include a practical calibration procedure for correcting mounting error in order to obtain more accurate spatial information and a refined human gait model for more accurate temporal information.

Forward Head Posture (FHP) is a common musculoskeletal disorder correlated with neck pain that affects a large percentage of the population. Research has shown that providing feedback for posture auto-correction can help combat FHP and reduce the associated neck pain. However, existing methods for head posture detection are immobile, invasive, and/or inaccurate. This paper presents the use and video-based validation of wireless inertial body sensors for FHP detection. In addition, the effectiveness of bio-feedback is evaluated.

Cost pressure is driving vendors of safety-critical systems to integrate previously distributed systems. One natural approach we have previous introduced is On-Demand Redundancy (ODR), which allows safety-critical and non-critical tasks, traditionally isolated to limit interference, to execute on shared resources. Our prior work has shown that relaxed dedication (RD), one ODR strategy which allows non-critical tasks (NCTs) to execute on idle critical task resources (CTRs), significantly increases NCT throughput. Unfortunately, there are circumstances under which, in spite of this opportunity, it is difficult to effectively schedule NCTs.

We introduce on-demand redundancy, a set of architectural techniques that leverage the tightly-coupled nature of components in systems-on-chip to reduce the cost of safety-critical systems. On-demand redundancy eases the assumptions that traditionally segregate the execution of critical and non-critical tasks (NCTs), making resources available for critical tasks at potentially arbitrary points in both space and time, and otherwise freeing resources to execute non-critical tasks when critical tasks are not executing. Relaxed dedication is one such technique that allows non-critical tasks to execute on critical task resources. Our results demonstrate that for a wide variety of applications and architectures, relaxed dedication is more cost-effective than a traditional approach that employs dedicated resources executing in lockstep. Applied to dual-modular redundancy (DMR), relaxed dedication exposes 73% more NCT cycles than traditional DMR on average, across a wide variety of usage scenarios.

Among the masking phenomena that render immunity to combinational logic circuits from soft errors, logical masking is the hardest to model and characterize. This is mainly attributed to the fact that the algorithmic complexity of analyzing a combinational circuit for such masking is quite high, even for modestly sized circuits. In this paper, we present a hierarchical statistical approach to characterize the vulnerability of combinational circuits given logical masking and error propagation. By conducting detailed analyses and fault simulations for circuits at lower levels, initial assumptions of 100% vulnerability with single random output errors are refined. Fault simulations performed on the ISCAS85 benchmark circuits and Kogge-Stone adders of various widths demonstrate the varied nature of vulnerability for different circuits. The analysis performed at the circuit level for a 32-bit Kogge-Stone adder is applied to a microarchitecture simulation to examine impact on system-level vulnerability.

Power consumption in many BSN devices is dominated by the wireless transmission of raw sensed data. On-node data reduction techniques can be employed to enhance energy efficiency but often come at the expense of application fidelity. This energy-fidelity relationship, however, is subject to both inter- and intra-individual variations, calling for dynamically adaptable on-node signal processing techniques that adjust key parameters based on real-time phenomena. This work presents the tools, methods, and framework for dynamic energy-fidelity optimization, including online data profiling for information content, on-node data rate reduction techniques, energy and resource profiling for executing those techniques, and application fidelity assessment. This approach is demonstrated on an inertial BSN platform using data collected in a clinical study of tremor. Compared to static data reduction settings that are based on patient-specific data profiling, dynamic energy-fidelity optimization through online profiling is shown to reduce energy by 76% for a given data distortion or reduce distortion by 90% for a given energy.

While many BSN applications require that sensor nodes be able to operate for extended periods of time, they also often require the wireless transmission of copious amounts of sensor data to a data aggregator or base station, where the raw data is processed into application-relevant information. The energy requirements of such streaming can be prohibitive, given the competing considerations of form factor and battery life requirements. Making intelligent decisions on the node about which data to store or transmit, and which to ignore, is a promising method of reducing energy consumption. Artificial neural network (ANN) classifiers are among several competitive techniques for such data selection. However, no systematic metrics exist for determining if an ANN classifier is suited for a particular resource constrained computing environment of a typical BSN node. An especially difficult task is assessing, at the design stage, which classifier architectures are feasible on a given resource-constrained node, what computational resources are required to execute a given classifier, and what classification performance might be achieved by a particular classifier on a given set of resources. This paper describes techniques for quantifying and predicting the performance of ANN classifiers on wearable sensor nodes using scalable synthetic test data. Additionally, the paper shows a comparison of synthetic data with gait data collected using an inertial BSN node, and classification results of the gait data using a cerebellar model arithmetic computer (CMAC) architecture show excellent agreement with theoretical predictions.

Semiconductor devices are becoming more susceptible to single event upsets (SEUs) as device dimensions, operating voltages and frequencies are scaled. The majority of architecture-, logic- and circuit-level techniques that have been developed to address SEUs in logic assume a single-point fault model. This will soon be insufficient as the occurrence of spatial multi-bit errors is becoming prevalent in highly scaled devices. In this paper, we explore this new fault model and evaluate the effectiveness of conventional fault tolerance techniques to mitigate such faults. We also extend the idea of bit interleaving in memory to logic bit slices and explore its utility as an approach to spatial multi-bit error mitigation in logic. We present a comparison of these techniques using a case study of a Brent-Kung adder at a 90-nm process.

Transient faults (also known as soft-errors) resulting from high-energy particle strikes on silicon are typically modeled as single bit-flips in memory arrays. Most Architectural Vulnerability Factor (AVF) analyses assume this model. However, accelerated radiation tests on static random access memory (SRAM) arrays built using modern technologies show evidence of clustered upsets resulting from single particle strikes. In this paper, these observations are used to define a scalable fault model capable of representing fault multiplicities. Applying this model, a probabilistic framework for incorporating vulnerability of SRAM arrays to different fault multiplicities into AVF is proposed. An experimental fault injection setup using a detailed microarchitecture simulation running generic benchmarks was used to demonstrate vulnerability characterization in light of the new fault model. Further, rigorous fault injection is used to demonstrate that conventional methods of AVF estimation overestimate vulnerability up to 7× for some structures.

Subthreshold digital circuits minimize energy per operation and are thus ideal for ultralow-power (ULP) applications with low performance requirements. However, a large range of ULP applications continue to face performance constraints at certain times that exceed the capabilities of subthreshold operation. In this paper, we give two different examples to show that designing flexibility into ULP systems across the architecture and circuit levels can meet both the ULP requirements and the performance demands. Specifically, we first present a method that expands on ultradynamic voltage scaling (UDVS) to combine multiple supply voltages with component level power switches to provide more efficient operation at any energy-delay point and low overhead switching between points. This system supports operation across the space from maximum performance, when necessary, to minimum energy, when possible. It thus combines the benefits of single-VDD, multi-VDD, and dynamic voltage scaling (DVS) while improving on them all. Second, we propose that reconfigurable subthreshold circuits can increase applicability for ULP embedded systems. Since ULP devices conventionally require custom circuit design but the manufacturing volume for many ULP applications is low, a subthreshold field programmable gate array (FPGA) offers a cost-effective custom solution with hardware flexibility that makes it applicable across a wide range of applications. We describe the design of a subthreshold FPGA to support ULP operation and identify key challenges to this effort.

Application-specific integrated circuits (ASICs) are physical implementations of algorithms, so implementation metrics are determined in large part by the algorithm specification. However, the system abstraction layers that have been developed to manage the ever-increasing complexity of digital systems separate algorithm designers from hardware designers, forcing the latter to work within the design space specified by the former, even for applications such as multimedia that do not have hard fidelity requirements. Designers typically employ informal iterative design to adjust fidelity, but a formal design methodology would increase designer efficiency and improve the quality of the solutions. This paper introduces such a methodology (and accompanying tool) that enables algorithm and implementation metrics to be co-optimized during early design exploration, opening the design space to include solutions that may provide, for example, significant performance improvements while only slightly compromising fidelity. Hierarchical dependency graphs (HDGs) are used to represent both the algorithm and the implementation architecture, providing a common interface through which algorithm designers and hardware designers can explore the collaborative space (ColSpace) together. Using the proposed technique, the ColSpace tool can trade off various metrics to find the best overall design while managing complexity with the HDG hierarchy. Two image processing case studies demonstrate that in ColSpace-optimized designs, latency savings can exceed fidelity losses, resulting in cost function reductions that would not have been possible without this co-optimization methodology.

The energy efficiency of a CMOS architecture processing dynamic workloads directly affects its ability to provide long battery lifetimes while maintaining required application performance. Existing scalable architecture design approaches are often limited in scope, focusing either only on circuit-level optimizations or architectural adaptations individually. In this paper, we propose a circuit/architecture co-design methodology called Panoptic Dynamic Voltage Scaling (PDVS) that makes more efficient use of common circuit structures and algorithm-level processing rate control. PDVS expands upon prior work by using multiple component-level PMOS header switches to enable fine-grained rate control, allowing efficient dithering among statically scheduled algorithms with sub-block energy savings. This way, PDVS is able to achieve a wide variety of processing rates to match incoming workload as closely as possible, while each iteration takes less energy to process than on architectures with coarser levels of rate control. Measurements taken from a fabricated 90 nm test chip characterize both savings and overheads and are used to inform PDVS synthesis decisions. Results show that PDVS consumes up to 34% and 44% less energy than Multi-VDD and Single-VDD systems, respectively.

Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connect DVS blocks to one of the available VDDsupplies. While power switches have been analyzed extensively for leakage power gating, proper design of power switches for DVS is less well understood. This paper characterizes power switches for DVS in terms of VDD-switching delay and VDD-switching energy. We show the impact of these switching overheads on a novel fine-grained DVS architecture and present an RC model that allows fast estimation of the overhead. Measurements of a DVS multiplier and adder on a 90 nm CMOS test chip validate the model. Our model and measurements confirm that power switched DVS can provide sufficiently low overhead to give energy savings with only one clock cycle spent at a lower voltage, making this approach a flexible and enticing option for embedded portable systems.

The increased process, voltage, and temperature (PVT) variability that comes with integrated circuit (IC) technology scaling has become a major problem in the semiconductor industry. In order to refine manufacturing processes and develop circuit design techniques to cope with variability, we must be able to accurately and precisely characterize the variations that occur. In this paper, we introduce a technique for characterizing combinational path delay variations by measuring a designer-controlled number of register-to-register delays in manufactured ICs with negative-skewed shadow registers. This technique enables delay measurements to be performed with at-speed tests that are run in parallel with and are orthogonal to other testing techniques, and therefore does not add combinatorial complexity to the testing process. This technique can be implemented cost-effectively on a large number of otherwise unobservable internal combinational paths to get accurate, precise data about delay variability.

Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature dependence of leakage power, circuit performance, IC package cost, and reliability. While many interconnect reliability models assume a constant temperature, this paper analyzes the effects of temporal and spatial thermal gradients on interconnect lifetime in terms of electromigration, and presents a physics-based dynamic reliability model which returns reliability equivalent temperature and current density that can be used in traditional reliability analysis tools. The model is verified with numerical simulations and reveals that blindly using the maximum temperature leads to too pessimistic lifetime estimation. Therefore, the proposed model not only increases the accuracy of reliability estimates, but also enables designers to reclaim design margin in reliability-aware design. In addition, the model is useful for improving the performance of temperature-aware runtime management by modeling system lifetime as a resource to be consumed at a stress-dependent rate

This paper presents an efficient method to find the optimal intra-task voltage/frequency scheduling for single tasks in practical real-time systems using statistical workload information. Our method is analytic in nature and proved to be optimal. Simulation results verify our theoretical analysis and show significant energy savings over previous methods. In addition, in contrast to the previous techniques in which all available frequencies are used in a schedule, we find that, by carefully selecting a subset of a small number of frequencies, one can still design a reasonably good schedule while avoiding unnecessary transition overheads.

This paper presents an optimal procrastinating voltage scheduling (OP-DVS) for hard real-time systems using stochastic workload information. Algorithms are presented for both single-task and multi-task workloads. Offline calculations provide real-time guarantees for worst-case execution, and online scheduling reclaims slack time and schedules tasks accordingly. The OP-DVS algorithm is provably optimal in terms of energy minimization with no deadline misses. Simulation results show up to 30% energy savings for single-task workloads and 74% for multi-task workloads compared to using a constant worst-case execution voltage. The complexity of the algorithm for multi-task workloads is linear to the number of tasks involved.

FPGA logic densities continue to increase at a tremendous rate. This has had the undesired consequence of increased power density, which manifests itself as higher on-die temperatures and local hotspots. Sophisticated packaging techniques have become essential to maintain the health of the chip. In addition to static techniques to reduce the temperature, dynamic thermal management techniques are essential. Such techniques rely on accurate on-chip temperature information. In this paper, we present the design of a system that monitors the temperatures at various locations on the FPGA. This system is composed of a controller interfacing to an array of temperature sensors that are implemented on the FPGA fabric. Such a system can be used to implement dynamic thermal management techniques. We cross validate the sensor readings with values obtained from HotSpot, a pre-RTL architectural level thermal modeling tool.

The design of quality digital systems depends on models that accurately evaluate various options in the design space against a set of prioritized metrics. While individual models for evaluating area, performance, reliability, power, etc. are well established, models combining multiple metrics are less mature. This paper introduces a formal methodology for comprehensively analyzing performance, area and reliability in the design of synchronous dataflow systems using a novel Markov Reward Model. A Markov chain system reliability model is constructed for various design options in the presence of possible component failures, and high-level synthesis techniques are used to associate performance and area rewards with each state in the chain. The cumulative reward for a chain is then used to evaluate the corresponding design option with respect to the metrics of interest. Application of the model to a benchmark DSP circuit provides insights into reliable synchronous dataflow system design.

Thermal effects are becoming a limiting factor in high-performance circuit design due to the strong temperature-dependence of leakage power, circuit performance, IC package cost and reliability. While many interconnect reliability models assume a constant temperature, this paper presents a physics-based model for estimating interconnect lifetime for any time-varying temperature/current profile. This model is verified with numerical solutions. With this model, we show that designers may be more aggressive with the temperature profiles that are allowed on a chip. In fact, our model reveals that when the temperature magnitude variation is small, average temperature (instead of worst-case temperature) can be used to accurately predict interconnect lifetime, allowing for significant design margin reclamation in reliability-aware design. Even when the variation of temperature magnitude is large, our model shows that using the maximum temperature is still too conservative for interconnect lifetime prediction. Therefore, our model not only increases the accuracy of reliability estimates, but also enables designers to consider more aggressive designs. This model is similarly useful for temperature-aware dynamic runtime management.

A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been developed to help reduce leakage in SRAM-based memory, in which the percent leakage power is especially acute. SRAM-based field programmable gate arrays (FPGAs) pose similar leakage problems, but their structure and function require different solutions. This paper introduces a low complexity post-processing approach to reducing FPGA leakage current by ground-gating off SRAM cells that are unused in a particular device configuration. The approach is general enough to apply to any device configuration, and results reveal that the significant leakage current reduction can be achieved with no delay penalty and acceptable area overhead.

editorial Free Access Share on Editorial: Special issue on dynamically adaptable embedded systems Editors: John Lach University of Virginia, Charlottesville, VA University of Virginia, Charlottesville, VAView Profile , Kia Bazargan University of Minnesota, Minneapolis, MN University of Minnesota, Minneapolis, MNView Profile Authors Info & Claims ACM Transactions on Embedded Computing SystemsVolume 3Issue 2pp 233–236https://doi.org/10.1145/993396.993397Published:01 May 2004Publication History 1citation926DownloadsMetricsTotal Citations1Total Downloads926Last 12 Months9Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Publisher SiteeReaderPDF

Concerned by the wall that Moore's Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device improvements. While significant advancements in nanotechnology devices have been achieved, much work is required to integrate these technologies into the existing design methodologies. Given that the physical design paradigm of each nanotechnology will be significantly different than that of traditional silicon circuits, the underlying cost functions used in optimization algorithms throughout the design abstraction hierarchy must be altered. Because nanotechnologies are not as well developed and understood as silicon devices, abstraction will initially result in less accurate models. However, if models are developed and augmented as nanotechnologies continue to evolve, the transition from CMOS-based design to nano-based design will be relatively seamless.This paper details the logic-level abstraction process for area minimization for one promising nanotechnology - quantum cellular automata (QCA). The model abstracts relative area costs, including interconnect area, for QCA devices, and it is integrated within existing multi-level logic synthesis techniques. Results validate the proposed approach of designing nano-based circuits with the traditional abstraction-based design methodology.

Despite recent advances, battery life continues to be a limiting factor in mobile multimedia systems. Significant energy savings can be achieved by adapting systems at runtime to match the execution requirements of different tasks. We introduce an online dynamic voltage/frequency scaling (DVS) feedback technique that reduces voltage and frequency to match the playback rate. A PI controller adjusts the decoder's speed to keep constant the occupancy of the buffer between the decoder and the display, effectively matching the average decode rate to the display rate without the need for any off-line profiling. MPEG simulation results show that this technique reduces decoder power consumption while providing strong real-time guarantees.

As the dominating CMOS technology is fast approaching a "brick wall," new opportunities arise for competing solutions. Nanoelectronics has achieved several breakthroughs lately and promises to overcome many of the limitations intrinsic to current semiconductor approaches. Most of the results in this area reported until now focus on devices and interconnect; this work goes several steps further and presents issues related to circuits and architecture. Based on proposed nanoscale interconnect and device structures, we explore the design space available to the nanoelectronic circuit designer and system architect.

This paper describes a formal feedback-control algorithm for dynamic voltage/frequency scaling (DVS) in a portable multimedia system to save power while maintaining a desired playback rate. Our algorithm is similar in complexity to the previously-proposed change-point detection algorithm [19] but does a better job of maintaining stable throughput and is not dependent on the assumption of an exponential distribution of the frame decoding rate. For approximately the same energy savings as reported by [19], our controller is able to keep the average frame delay within 10% of the target more than 90% of the time, whereas the change-point detection algorithm kept the average frame delay with 10% of the target only 70% or less of the time executing the same workload.

The coupling capacitances between on-chip bus lines become dominant in deep-submicron technologies. Coding to reduce the switching activity of the individual lines was enough to reduce power on buses in older technologies, but new coding techniques that reduce the coupling activity between lines are needed for deep-submicron buses. One such coding technique uses the simple observation that coupling capacitances are always charged and discharged by activity on neighboring bus lines, where one line has an odd number and the other has an even number (if bus lines are numbered "in-order"). We thus propose to reduce the coupling activity by independently controlling the odd and even bus lines with two separate lines, the Odd Invert, and Even Invert line, respectively. We obtain significant reductions in power simply by comparing the coupling activity for the four possible cases of the Odd and Even Invert lines (00, 01, 10, 11), and then choosing the value with the smallest coupling activity to transmit on the bus. Even after encoding, the coupling activity for a pair of bus lines is still strongly dependent on the data. In particular the toggling sequences 01→10 and 10→01 result in 4 times more coupling energy dissipation than other coupling events. We thus propose a targeted Two-Phase transfer in order to reduce total power only on the pairs of lines that carry such toggling events.

Digital system designs are the product of valuable effort and know-how. Their embodiments, from software and hardware description language program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms to protect the rights of IP producers and owners. This paper establishes principles of watermarking-based IP protection, where a watermark is a mechanism for identification that is: (1) nearly invisible to human and machine inspection; (2) difficult to remove; and (3) permanently embedded as an integral part of the design. Watermarking addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. We survey related work in cryptography and design methodology, then develop desiderata, metrics, and concrete protocols for constraint-based watermarking at various stages of the very large scale integration (VLSI) design process. In particular, we propose a new preprocessing approach that embeds watermarks as constraints into the input of a black-box design tool and a new postprocessing approach that embeds watermarks as constraints into the output of a black-box design tool. To demonstrate that our protocols can be transparently integrated into existing design flows, we use a testbed of commercial tools for VLSI physical design and embed watermarks into real-world industrial designs. We show that the implementation overhead is low-both in terms of central processing unit time and such standard physical design metrics as wirelength, layout area, number of vias, and routing congestion. We empirically show that the placement and routing applications considered in our methods achieve strong proofs of authorship and are resistant to tampering and do not adversely influence timing.

As current computer-aided design (CAD) tool and very large scale integration technology capabilities create a new market of reusable digital designs, the economic viability of this new core-based design paradigm is pending on the development of techniques for intellectual property protection. This work presents the first technique that leverages the unique characteristics of field-programmable gate arrays (FPGAs) to protect commercial investment in intellectual property through fingerprinting. A hidden encrypted mark is embedded into the physical layout of a digital circuit when it is placed and routed onto the FPGA. This mark uniquely identifies both the circuit origin and original circuit recipient, yet is difficult to detect and/or remove, even via recipient collusion. While this approach imposes additional constraints on the backend CAD tools for circuit place and route, experiments indicate that the performance and area impacts are minimal.

Simulations for modern designs are often performed on Field Programmable Gate Array technology in a functional test and debugging process known as emulation, allowing for more complex simulations than possible in software. One drawback to emulation is the lengthy time spent in the back-end CAD tools for each debugging iteration, including debugging changes and the introduction of control and observation logic. We have developed a technique that confines the re-place-and-route area to only the portions of the design affected by the introduction of the test logic and by the debugging changes. Therefore, the back-end CAD effort for error detection, localization, and correction is reduced. This benefit is achieved by partitioning the design at the physical level into independent blocks, and the test logic and design changes are localized to the affected blocks. The result is a shortened time between debugging iterations, and thus a shortened time-to-market for the design.

The expanded use of field programmable gate arrays (FPGA) in remote, long life, and system-critical applications requires the development and implementation of effective, efficient FPGA fault-tolerance techniques. FPGA have inherent redundancy and in-the-field reconfiguration capabilities, thus providing alternatives to standard integrated circuit redundancy-based fault-recovery techniques. Runtime reliability can be enhanced by using such unique features. Recovery from permanent logic and interconnect faults without runtime computer-aided design (CAD) support can be efficiently performed with the use of fine-grained and physical design partitioning. Faults are localized to small partitioned blocks that have fixed interfaces to the surrounding portions of the design, and the affected blocks are reconfigured with previously generated, functionally equivalent block instances that do not use the faulty resources. This technique minimizes the post-fault-detection system downtime, while requiring little area overhead. Only the finely located faulty portions of the FPGA are removed from use. In addition, the end user need not have access to CAD tools, making the algorithm completely transparent to system users. This approach has been efficiently implemented on a diverse set of FPGA architectures. The algorithm's flexibility is also apparent from the variable emphases that can be placed on system reliability, area overhead, timing overhead, design effort, and system memory. Given user-defined emphases, the algorithm can be modified to specific application requirements. Experiments using random s-independent and s-correlated fault models reveal that the approach enhances system reliability, while minimizing area and timing overhead.

A number of researchers have proposed using digital marks to provide ownership identification for intellectual property. Many of these techniques share three specific weaknesses: complexity of copy detection, vulnerability to mark removal after revelation for ownership verification, and mark integrity issues due to partial mark removal. This paper presents a method for watermarking field programmable gate array (FPGA) intellectual property (IP) that achieves robustness by responding to these three weaknesses. The key technique involves using secure hash functions to generate and embed multiple small marks that are more detectable, verifiable, and secure than existing IP protection techniques.

No abstract available.

Digital system designs are the product of valuable effort and knowhow. Their embodiments, from software and HDL program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms to protect the rights of IP producers and owners. This paper establishes principles of watermarkingbased IP protection, where a watermark is a mechanism for identification that is (i) nearly invisible to human and machine inspection, (ii) difficult to remove, and (iii) permanently embedded as an integral part of the design. We survey related work in cryptography and design methodology, then develop desiderata, metrics and example approaches -- centering on constraint-based techniques -- for watermarking at various stages of the VLSI design process. 1 Introduction The advance of processing technology has led to a rapid increase in IC design complexity. The economic drivers are compelling: only by put...

While system reliability is conventionally achieved through component replication, we have developed a fault-tolerance approach for FPGA-based systems that comes at a reduced cost in terms of design time, volume, and weight. We partition the physical design into a set of tiles. In response to a component failure, we capitalize on the unique reconfiguration capabilities of FPGAs and replace the affected tile with a functionally equivalent tile that does not rely on the faulty component. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors, this approach allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of realiability with low timing and hardware overhead.

Abstract – This work presents the first known attempt to leverage the unique characteristics of FPGAs to protect commercial investments in intellectual property. A watermark is applied to the physical layout of a digital circuit when it is mapped into an FPGA. This watermark uniquely identifies the circuit origin and yet is difficult to detect. While this approach imposes additional constraints, experiments involving a number of large complex designs indicate that the performance impact is small. 1

Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume, and weight. We have developed a new fault-tolerance approach that capitalizes on the unique reconfiguration capabilities of field programmable gate arrays (FPGA's). The physical design is partitioned into a set of tiles. In response to a component failure, a functionally equivalent tile that does not rely on the faulty component replaces the affected tile. Unlike application specific integrated circuit (ASIC) and microprocessor design methods, which result in fixed structures, this technique allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead.