Demo Data from EDBT 2026 / reviewers in the wild / expert
Bjorn Breidegard
dblp:07/319
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 56% Processor architecture and microarchitecture · 28% High-performance computing · 8% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip
bus-based interconnection |
0.0 | 1 | 1983 | A Communication Structure for a Multiprocessor Computer with Distributed Global Memory · ISCA 1983 |
Interconnection networks and networks-on-chip › bus-based interconnection
global bus |
0.0 | 1 | 1983 | A Communication Structure for a Multiprocessor Computer with Distributed Global Memory · ISCA 1983 |
Processor architecture and microarchitecture › multiprocessor architecture
multiprocessor design |
0.0 | 1 | 1983 | A Communication Structure for a Multiprocessor Computer with Distributed Global Memory · ISCA 1983 |
High-performance computing
distributed memory systems |
0.0 | 1 | 1983 | A Communication Structure for a Multiprocessor Computer with Distributed Global Memory · ISCA 1983 |
Distributed systems
global memory |
0.0 | 1 | 1983 | A Communication Structure for a Multiprocessor Computer with Distributed Global Memory · ISCA 1983 |
Methods — techniques the papers use, named apart from their topics
prototyping · 0.0experimentation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | A Communication Structure for a Multiprocessor Computer with Distributed Global MemoryabstractAn experimental multiprocessor computer was designed and built in order to explore the feasibility of certain internal communication mechanisms. The system consisted of seven processing elements, each containing a part of the global memory connected to a local bus. For each processor the global memory is seen as one single, linearly addressable structure. The processing elements were all connected to a common, global bus, consisting of three separate busses in order to increase the capacity. A bus selection unit was designed, capable of making a unique bus selection for each request, within a fraction of a memory cycle. The experiments have shown that communication structures based on distributed global memory and global bus systems can be used efficiently for medium scale systems. Lars H. Philipson, Bo Nilsson, Bjorn Breidegard |
ISCA | 3 |