Article Free Access Share on HPF compiler for the AP1000 Authors: Tatsuya Shindo Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, Japan Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, JapanView Profile , Hidetoshi Iwashita Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, Japan Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, JapanView Profile , Tsunehisa Doi Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, Japan Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, JapanView Profile , Junichi Hagiwara Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, Japan Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, JapanView Profile , Shaun Kaneshiro Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, Japan Fujitsu Ltd., 1015 Kamikodanaka, Nakahara, Kawasaki 211, JapanView Profile Authors Info & Claims ICS '95: Proceedings of the 9th international conference on SupercomputingJuly 1995 Pages 190–194https://doi.org/10.1145/224538.224560Published:03 July 1995Publication History 4citation139DownloadsMetricsTotal Citations4Total Downloads139Last 12 Months5Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The scalability of distributed-memory parallel computers makes them attractive candidates for solving large-scale problems. New languages, such as HPF, FortranD, and VPP Fortran, have been developed to enable existing software to be easily ported to such machines. Many distributed-memory parallel computers have been built, but none of them support the mechanisms required by such languages. We studied the mechanisms required by parallelizing compilers and proposed a new architecture to support them. Based on this proposed architecture, we developed a new distributed-memory parallel computer, the AP1000+, which is an enhanced version of the AP1000. Using scientific applications in VPP Fortran and C, such as NAS parallel benchmarks, we simulated the performance of the AP1000+.

This paper proposes twisted data layout as a novel and efficient data layout technique for distributed memory parallel processors (DMPP). Data layout is an important aspect in efficiently executing a parallel program on DMPPs. The optimal data layout pattern for an array may differ throughout the program. Twisted data layout can be used to resolve the conflicts among the optimal array distributions in a special case. Experimental results on the AP1000 multicomputer measure the performance of the twisted data layout scheme.

A novel general routing algorithm is presented. Each net is routed to minimize the cost function defined by a weighted sum of penalties. Two types of design rule violations, touches and crosses, are factors of the cost function. Using these violations enables the algorithm to achieve 100% completion even when routing problems have nets which must be considered simultaneously. This type of problem could not be routed completely by conventional rip-up routers. The algorithm was implemented on a newly developed massively parallel computer. Experimental results on Burstein's difficult switch box problem and several small printed circuit boards show that the algorithm is as powerful as a human expert designer. >