Demo Data from EDBT 2026 / reviewers in the wild / expert
Jörn Schneider
dblp:07/3458
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2013
0000-0001-8452-9216ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Embedded and real-time systems · 87% Processor architecture and microarchitecture · 6% Memory systems · 6% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Embedded and real-time systems › real-time scheduling › fixed-priority scheduling
fixed-priority preemptive scheduling |
0.0 | 1 | 2000 | Cache and Pipeline Sensitive Fixed Priority Scheduling for Preemptive Real-Time Systems · RTSS 2000 |
Embedded and real-time systems
real-time scheduling |
0.0 | 1 | 2000 | Cache and Pipeline Sensitive Fixed Priority Scheduling for Preemptive Real-Time Systems · RTSS 2000 |
Embedded and real-time systems › real-time scheduling › schedulability analysis
response time analysis |
0.0 | 1 | 2000 | Cache and Pipeline Sensitive Fixed Priority Scheduling for Preemptive Real-Time Systems · RTSS 2000 |
Embedded and real-time systems
worst-case execution time analysis |
0.0 | 1 | 2000 | Cache and Pipeline Sensitive Fixed Priority Scheduling for Preemptive Real-Time Systems · RTSS 2000 |
Memory systems
cache |
0.0 | 1 | 2000 | Cache and Pipeline Sensitive Fixed Priority Scheduling for Preemptive Real-Time Systems · RTSS 2000 |
Processor architecture and microarchitecture
pipelining |
0.0 | 1 | 2000 | Cache and Pipeline Sensitive Fixed Priority Scheduling for Preemptive Real-Time Systems · RTSS 2000 |
Methods — techniques the papers use, named apart from their topics
schedulability analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | SimTrOS: A heterogenous abstraction level simulator for multicore synchronization in real-time systems
Michael Bohn, Jörn Schneider, Christian Eltges |
J. Syst. Archit. | 2 |
| 2010 | Towards an Evaluation Infrastructure for Automotive Multicore Real-Time Operating Systems
Jörn Schneider, Christian Eltges |
ISoLA (2) | 1 |
| 2000 | Cache and Pipeline Sensitive Fixed Priority Scheduling for Preemptive Real-Time SystemsabstractCurrent schedulability analyses for preemptive systems consider cache behaviour by adding preemption-caused cache reload costs. Thereby, they ignore the fact that delays due to cache misses often have a reduced impact because of pipeline effects. In this paper, these methods are called isolated. Pipeline-related preemption costs are not considered at all in current schedulability analyses. This paper presents two cache- and pipeline-sensitive response time analysis methods for fixed-priority preemptive scheduling. The first is an isolated method. The second method incorporates the preemption-caused cache costs into the worst-case execution time (WCET) of the preempted task. This allows for the compensation of delays due to cache misses by pipeline effects. It is shown that the applicability of isolated approaches is limited to a certain class of CPUs. Practical experiments are used to compare both methods. Jörn Schneider |
RTSS | 1 |