The field-deployed Internet-of-Things (IoT) sensor nodes are powered by rechargeable batteries. The nodes are equipped with energy harvesters to harvest energy from the environment to replenish the batteries and continue the sensing operations. However, due to the high energy consumption of the power-hungry sensors, the nodes still suffer from energy depletion issues. Towards a green IoT system, an energy aware adaptive sensing algorithm is proposed in this paper. For a multi-sensing node, a learning-aided smart sensing strategy is developed to find a set of optimal sensors to be activated in the next measurement cycle depending on the cross-correlation factors and the sensing energy consumption. The parameters of inactive sensors are predicted from cross-correlated parameters of active sensors using Gaussian process regressor model. Further, the algorithm is implemented in a solar powered air pollution monitoring system to analyze the performance of this method. The proposed method saves 68% energy of the node compared to the nearest competitive method, while the sensing error is within the limit.

This paper reports the measurements of thermo-mechanical package stress effects on High Resistivity Polysilicon Resistors (HRI-poly) and presents guidelines for the optimal placement of such resistors to minimize variations due to stress. The chip center is considered the radial axis, and nine HRI resistors are placed at different radii and angles from it. The test structures are fabricated in a 180nm CMOS process. Thermo-mechanical package stress affects the value of resistors depending on their location. It is observed that the resistors placed close to the chip center and aligned perpendicular to the radial line have the least effective mismatch due to stress/temperature. The resistors placed close to the chip edge, and parallel to the radial line have the maximum effective mismatch due to temperature/stress. The paper presents the analysis along with the guidelines for placing the resistors.

We present an ultra-low-power band-gap reference-based regulator and a unique method of generating a proportional-to-absolute-temperature (PTAT) voltage and a PTAT current. The PTAT current is used to generate a BJT complementary-to-absolute-temperature (CTAT) voltage. This CTAT voltage and PTAT voltage are added to generate a regulated output voltage in the negative feedback loop to drive the load. The output of the proposed regulator is temperature stable from −20° C to 85° C with a mean variation of less than 20 ppm/° C. The proposed technique eliminates the need for an additional start-up circuitry, which is mandatory for conventional architectures. The 1.18 V output voltage regulator, designed in a 180-nm CMOS process, has a simulated line regulation of 0.1 %/V with a power consumption of 15 nW at room temperature. The proposed regulator can drive the load from 0 to 30 mA.

Wireless sensors networks (WSNs) are gaining enormous attention for monitoring physical conditions in various application. WSNs equipped with power-hungry senors often suffer from energy sustainability. Hence, an efficient smart sensing approach is required to enhance the energy sustainability of such WSNs. A wireless node equipped with a sensor monitoring the variation of a particular parameter in time often exhibits high temporal correlation that can be studied to smartly sense the parameter. To optimize the energy consumption of these sensors and increase the network lifetime, this paper presents a learning- based adaptive sampling framework that explores the sparsity in the time series data and finds optimal sampling instants for the next measurement cycle. Principal component analysis (PCA) is used to sparsify the time domain signal and the sparse signal is reconstructed from its low-dimensional signal using the sparse Bayesian learning (SBL) method. An optimization function is formed that solves the trade-off between accuracy and energy consumption and finds the optimal sampling instants for the next measurement cycle. The performance of the proposed adaptive sampling framework is tested on air pollution monitoring dataset. The simulation results validate the energy efficiency of the proposed method. Compared to the existing adaptive sampling algorithms the proposed learning-based algorithm saves up to 58% energy with a marginally higher computational complexity while maintaining an acceptable range of sensing error.

In this paper, a curvature-compensated bandgap reference circuit is presented which generates 0.538V from 0.85V supply voltage. The PTAT voltage generated in the bandgap core is added to the partial CTAT voltage to generate the sub-bandgap reference, reducing the CTAT current mirror mismatch. Furthermore, this architecture eases the opamp's requirements on offset and flicker noise significantly and doesn't require sophisticated techniques, such as chopping. A novel curvature compensation scheme is proposed and validated across PVT simulations and achieves 12 ppm/°C with a single point trim. The proposed bandgap consumes a power of 15 μW and occupies an area of 7315 μm2in TSMC 28nm.

A 900-MHz 1.2-V 4.36-mA low-noise amplifier (LNA) with a minimum of 0.92-dB noise figure (NF) at 868 MHz, -12-dBm IIP3, with one inductor (external) is demonstrated. The circuit achieves narrowband input matching on a wideband LNA without inductive degeneration. A new half-cascoding technique is used to improve the input matching (S11) while simultaneously achieving sub-1-dB NF performance. The 0.13-μm CMOS LNA is fabricated with embedded electrostatic discharge (ESD) protection diodes that add 60 and 80-fF loads at the RF input and output ports. At 868 MHz, the packaged LNA has a measured input return loss (S11) of -18 dB and the transmission gain (S21) of 14.2 dB. At 900 MHz, the LNA has a measured NF of 0.98 dB. The LNA (excluding the buffer) occupies an area of 0.047 mm2. The chip passes the human body model (HBM) test with an ESD zap of 2.5 kV within 10% margin of its prezap I-V characteristics, under JEDEC standards. Multiple packaged chips were characterized with no perceptible difference in performance, indicating a robust design.

This paper presents a gain-boosting technique for two-port N-path band-pass filters (BPFs) based on the principle of discrete-time parametric amplification in MOS devices. The proposed technique also acts as a noise figure (NF) reduction technique due to the low-noise amplification before the output commutation. Analytical expressions for gain, NF, and input impedance of the proposed parametrically gain-boosted N-path BPF are derived using linear periodically time-variant (LPTV) network analysis and have been verified through simulations. The measurement results of a pseudo-differential eight-path BPF, implemented in a 180 nm CMOS technology, are presented. The center frequency of the implemented filter is tunable from 0.05 GHz to 0.4 GHz with a Q varying from 4 to 18. The gain of the filter is programmable with the input common-mode voltage. At 0.4 GHz, the filter achieves a variable gain of 2-8 dB over the input common-mode range of 0.55 V to 0.85 V. At every tuned frequency, the filter has a peak gain ≥8 dB, NF0 dBm. It is also shown in simulations that the proposed gain-boosting technique reduced the NF of the filter by >2.2 dB while consuming a dynamic power in the range of 3.8-31 mW per filter.

We present an ultra-low-power fractional bandgap-based voltage reference and a unique method of generating a small proportional-to-absolute-temperature (PTAT) current. The PTAT current is used to generate a BJT complementary-to-absolute-temperature (CTAT) voltage. We have achieved temperature compensation of the generated reference voltage by subtracting a sub-threshold MOS CTAT voltage from the BJT CTAT voltage. The difference between the two CTAT voltages is temperature stable from -50°C to 85°C with a mean variation of less than 95 ppm/°C measured across chips, without any additional trim. The proposed technique eliminates the need for additional start-up circuitry, which is mandatory for conventional architectures. The 260-mV voltage reference designed in a 180-nm CMOS process has a measured line regulation of 0.23 %/V and consumes 1 nW at room temperature.

A temperature compensated under voltage lockout (UVLO) circuit for ultra-low power applications is presented. The UVLO operation is achieved using two transistors with different threshold voltages and a source follower. The difference in the thresholds of the two transistors is used to create a reference voltage. As the supply voltage rises, the generated reference voltage tracks the supply till its designed voltage value and thereafter becomes a constant. This reference voltage is applied to a self-referenced common-source stage and is further amplified by CMOS inverters to arrive at a decision to lock out the supply or not. The designed UVLO consumes 200 pA of current at 1.8 V supply. The measured low-to-high trip points (LHTP) and high-to-low trip points (HLTP) are 1.28 V and 1.12 V with a variability of 208 ppm/°C and 200 ppm/°C respectively. These trip points are programmable from 1.1 V to 1.4 V in steps of 100 mV. The design occupies 0.00723 mm2in standard 180 nm CMOS.

We show that the output impedance of an integrated LNA need not to be matched to 50 Ω for measurement purposes. The result is true for LNAs, both stand-alone or otherwise, that are designed to drive voltage-input or current-input mixers. We show that 50 Ω output impedance matching is detrimental to the performance of the LNA. A theoretical bound for the output impedance of an LNA is given, based on stability. We have inferred that proper design of a second-stage voltage buffer after the LNA can help with accurate measurements of the noise figure (NF) and gain of the LNA, with minimal impact on the core LNA specifications. A 5 Ω output impedance of the LNA-buffer stage, as opposed to 50 Ω, can improve the NF of reported LNAs by over 1 dB. A 900 MHz LNA with a source follower (SF) as a voltage buffer is implemented as an example in a 130-nm CMOS process. The SF with its biasing circuitry occupies an active area of 0.014 mm2. Measurement results show that with a mismatched low output impedance (30 Ω as opposed to 50 Ω), the NF and the gain of the LNA improves by 0.2 dB and 0.8 dB respectively, when compared with the matched output results.

This paper presents a continuous time sigma delta ADC for 50 MHz bandwidth with 80 dB resolution, which overcomes the shortcomings of known architectures. It incorporates a 5 bit flash ADC as a quantizer with a current steering feedback DAC employing dynamic element matching. The main feedback path and the fast feedback path around the quantizer have shifted delays to compensate for the excess loop delay. The architecture uses 28 nm FD-SOI technology with flipped well transistors having forward body bias. Circuit simulations predict a power consumption of 24 mW at a 1.0 V supply voltage, and state-of-the-art Schreier FOM of 173 dB.

A clock and data recovery (CDR) module in 90nm CMOS, for a 10Gbps serial link, integrated with a -18dB attenuation channel, is presented. A novel dual-loop CDR with separate charge pumps for high-gain frequency acquisition, and low-gain phase tracking has been introduced. The CDR utilizes a full rate architecture with a single VCO along with a selection logic for switching to the desired charge pump, resulting in a 4.2mW power consumption from the VCO. A current-steering charge pump with DCVSL inputs reduced the glitches in the up and down currents thereby reducing the ripples on the control voltage to 1mV in the locked condition. An rms and peak periodic jitter of 0.382ps and 0.759ps respectively were achieved with a PRBS sequence of 27bits, resulting in a design compliant with SONET OC-192 specifications.

A general technique for synthesis of concurrent multi-band matching networks is proposed. The proposed design technique can be adapted to any matching strategy (noise match or conjugate match using L-match, II-match or any other topology), for multiple frequencies. Detailed design procedures are outlined for dual-band and quad-band matching networks with the help of design examples. A prototype circuit board for a quad-band matching network has been realized with discrete components and laboratory measurement results are presented.

A high speed pseudo differential three stage operational amplifier has been implemented using a feed-forward compensation technique in a standard 0.13 μm CMOS technology. The three stage inverter based op-amp with feed-forward compensation achieves 11 GHz of unity gain bandwidth for a nominal power consumption 18 mW, and exhibits 39 dB of DC gain with phase margin of 62° when driving a differential load of (2×300 fF) at a 1.2 V power supply voltage. At a power supply voltage as low as 0.4 V, the same circuit consumes 0.1 mW and achieves 79 MHz of unity gain bandwidth. The proposed op-amp achieves a figure of merit (FOM) [1] of 440 at 1.2 V, and 190 at 0.4 V.

This work presents a feed-forward technique to reduce the third order harmonic distortion of a parametric amplifier. A prototype design of an nMOS based differential parametric amplifier with supporting circuits were integrated on a standard 0.13 μm CMOS technology. A comparison between a regular parametric amplifier, and a parametric amplifier with feed-forward distortion cancellation, demonstrates a mean reduction of third order harmonic distortion of -13 dB. This comes at a cost of a maximum gain reduction of 0.9 dB.

This paper estimates the feasibility of operating field sensors using otherwise unwanted radio frequency (RF) energy in a wireless ad hoc sensor network. In the traditional concept, an exposed node is kept from any communication activities during a neighbor's transmission. To save energy, the node may go to sleep mode during its inactivity period. In contrast, it is proposed that whenever a node is not communicating it should attempt to collect energy from the ongoing transmissions in its vicinity. A two-tier network is considered with the field sensor nodes having rudimentary communication (transmission) functionality at the first tier and the routing-capable nodes at the second tier. Via geometric probabilistic analysis, aided by network simulations, the conditions on rectification efficiency and transmission duty cycle of network RF energy operated field nodes are derived for their uninterrupted processing and transmission activities.