Demo Data from EDBT 2026 / reviewers in the wild / expert
John D. Bunda
dblp:07/4368
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › instruction set architecture › ISA specification
instruction encoding |
0.0 | 1 | 1993 | 16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors · ISCA 1993 |
Processor architecture and microarchitecture › instruction set architecture
instruction set design |
0.0 | 1 | 1993 | 16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors · ISCA 1993 |
Processor architecture and microarchitecture › pipelining
pipelined processor |
0.0 | 1 | 1993 | 16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors · ISCA 1993 |
Processor architecture and microarchitecture
instruction fetch |
0.0 | 1 | 1993 | 16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors · ISCA 1993 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1993 | 16-Bit vs. 32-Bit Instructions for Pipelined MicroprocessorsabstractIn any stored-program computer system, information is constantly transferred between the memory and the instruction processor. Machine instructions are a major portion of this traffic. Since transfer bandwidth is a limited resource, inefficiency in the encoding of instruction information (low code density) can have definite hardware and performance costs. John D. Bunda, Donald S. Fussell, Roy M. Jenevein, William C. Athas |
ISCA | 1 |