In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in Koren and Stapper (1989); one of the proofs presented in this paper is valid for any defect-tolerant IC, while the other one is valid for defect-tolerant ICs with two levels of hierarchy.>

We present a method to accelerate the search for the number of spares to be included in defect tolerant integrated circuits. Our method is obtained by bringing two modifications to a conventional evaluation method. The main motivations behind the development of this method are: the possibilities offered by the implementation of defect tolerance, the existence of many yield models, which may predict different results in terms of optimum number of spares, and the fact that some models are very compute intensive. The modeling methods leading to several usual yield models are briefly presented. We also present results showing that our method is valid for a wide range of parameters. However, this method can be applied to all yield models considered and it can significantly reduce the time spent in the search for the best possible reconfiguration strategies.>