Elasticity of cloud computing eases the burden of capacity planning. Cloud computing users dynamically provision IT resources tracking their fluctuating demand, and only pay for their usage. Therefore, cloud computing essentially shifts the burden of capacity planning from user's side to provider's side. On the other hand, providers take this burden with the optimistic assumption that diverse workloads from various users will flatten the overall demand curve. However, this optimistic hypothesis has not been proved yet in the real world cases. In fact, counter evidences have been raised. December 2009, Amazon Web Services (AWS), a leading infrastructure cloud service provider, started to offer a real-time pricing for computing resources -- Amazon EC2 Spot Instances (SIs). Real-time pricing, in principle, encourages users to shift their flexible workloads from provider's peak hours to off-peak hours with monetary incentives. Interestingly, from our observation on AWS's one-year SI price history datasets, we conclude that the observed monetary incentive is not large enough to motivate users to shift their workloads. It is reasonable for users to choose SIs over on-demand instances because SIs are 52.3% cheaper on average. After that, shifting the workload to cheaper period provides only 3.7 % additional cost savings at best. Moreover, both average cost savings and price fluctuation have not been meaningfully changed over time.

Chip-multiprocessors are quickly becoming popular in embedded systems. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded application development for such systems. Transactional memory (TM) promises to simplify concurrency management in multithreaded applications by allowing programmers to specify coarse-grain parallel tasks, while achieving performance comparable to fine-grain lock-based applications. This paper presents ATLAS, the first prototype of a CMP with hardware support for transactional memory. ATLAS includes 8 embedded PowerPC cores that access coherent shared memory in a transactional manner. The data cache for each core is modified to support the speculative buffering and conflict detection necessary for transactional execution. The authors have mapped ATLAS to the BEE2 multi-FPGA board to create a full-system prototype that operates at 100MHz, boots Linux, and provides significant performance and ease-of-use benefits for a range of parallel applications. Overall, the ATLAS prototype provides an excellent framework for further research on the software and hardware techniques necessary to deliver on the potential of transactional memory

Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithreaded application development. To address this challenge, it is necessary to co-develop new CMP architecture with novel programming models. Currently, architecture research relies on software simulators which are too slow to facilitate interesting experiments with CMP software without using small datasets or significantly reducing the level of detail in the simulated models. An alternative to simulation is to exploit the rich capabilities of modern FPGAs to create FPGA-based platforms for novel CMP research. This paper presents ATLAS, the first prototype for CMPs with hardware support for Transactional Memory (TM), a technology aiming to simplify parallel programming. ATLAS uses the BEE2 multi-FPGA board to provide a system with 8 PowerPC cores that run at 100MHz and runs Linux. ATLAS provides significant benefits for CMP research such as 100x performance improvement over a software simulator and good visibility that helps with software tuning and architectural improvements. In addition to presenting and evaluating ATLAS, we share our observations about building a FPGA-based framework for CMP research. Specifically, we address issues such as overall performance, challenges of mapping ASIC-style CMP RTL on to FPGAs, software support, the selection criteria for the base processor, and the challenges of using pre-designed IP libraries.