Chin-Yen Ho

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dblp:07/5514 · DBLP profile ↗

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1ranked-venue papers

0as first author

0since 2021 · last 1996

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Electronic design automation physical design	1	1996	New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing · DAC 1996
Electronic design automation › physical design › routing › steiner tree construction rectilinear steiner tree	1	1996	New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing · DAC 1996
Electronic design automation › physical design routing	1	1996	New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing · DAC 1996
Electronic design automation › physical design › interconnect optimization wire sizing	1	1996	New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing · DAC 1996
Electronic design automation › timing analysis › interconnect delay estimation elmore delay	1	1996	New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing · DAC 1996
Electronic design automation timing analysis	1	1996	New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing · DAC 1996

Methods — techniques the papers use, named apart from their topics

area/delay tradeoff curve · 0.0

Year	Publication	Venue	Position
1996	New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing abstract We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model.Our algorithms represent a departure f r om previous approaches in that we derive an explicit area/delay tradeo curve.We achieve this goal by limiting the solution space to the set of topologies induced b y a p ermutation on the sinks of the net.This constraint allows ecient identi cation of optimal solutions while still providing a rich solution space.We also incorporate simultaneous wire sizing.Our technique consistently p r o duces topologies equalling the performance o f previous approaches with substantially less area overhead. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho	DAC	4