Quantum computing is a compelling new technology that is becoming increasingly practical as time progresses. Quantum computers have the potential to solve problems of great complexity and magnitude across many different industries, utilizing appropriate quantum algorithms. Given the evolving stage of quantum computing, characterized by a limited number of operational quantum computers that demand extensive cooling, face decoherence issues, and incur significant fabrication costs, there exists a pronounced need for quantum computer simulators. In this work, a reconfigurable closed-loop CBRAM crossbar system has been developed for the execution and acceleration of quantum algorithm simulation, leveraging analog in-memory computing. The circuit supports a universal set of quantum gates representation, and through its reprogramming capabilities and feedback loop, can compute any quantum algorithm. To demonstrate its functionality, the 3-qubit Grover algorithm is executed on the proposed circuit. Building on the extensive circuit simulation, a comparative analysis of power and speed between the proposed nanoelectronic circuit and conventional hardware has been conducted, demonstrating the high efficiency and performance gains, followed by a scalability analysis. Furthermore, a framework has been developed that supports the design of custom closed-loop memristive crossbars through a graphical user interface (GUI), providing the user with the capability to execute quantum algorithms and examine the programming and computations of the circuit, assisting with the realization of a hardware prototype.

This paper presents the applicability of a mycelium-inspired reservoir network through an innovative extension of the Memristive Oscillating Cellular Automata (MOCA) circuit-based network. Drawing on the adaptive, self-organizing properties of mycelium, this MOCA grid employs SiNx-based RRAMs to form reconfigurable, dynamic connections that replicate mycelial network behaviors. Using the Stanford-PKU RRAM model, the non-linear properties of the fabricated devices have been characterized, establishing a flexible reservoir network capable of transforming and encoding input signals. The network has been evaluated, demonstrating small-world characteristics, including high clustering and short average path lengths, critical for effective information propagation and complex local dynamics. The resulting adaptable circuit offers a scalable foundation for future applications in bioinspired reservoir computing.

Mycelium, the vegetative structure of fungi, exhibits complex electrical signaling patterns when stimulated that resemble neural-like activity, which can be leveraged for bio-inspired computing and sensing applications. To replicate this activity, a 100x100 grid-based circuit has been designed capable of spiking behavior and adaptable configuration thanks to memristive technology aligned with fabricated devices, mimicking the dynamics seen in mycelial networks. Simulations have been carried out to demonstrate that the memristive grid successfully replicates key aspects of mycelium’s electrical activity recorded from experimental setups, including response to environmental stimuli, spiking signal propagation, and eradication.

Abstract Mycelium, the intricate vegetative network of fungi, has emerged as a promising candidate within the realm of engineered living materials (ELMs). While its intriguing structural and electrical properties highlight its potential, mycelium growth is highly sensitive to environmental conditions. To bridge this gap, a robust framework was developed to both model mycelium growth and explore its computational capabilities. This framework uses a cellular automata (CA) approach, enhanced with reaction-diffusion (RD) processes, to simulate mycelium growth under diverse environmental conditions. This configuration, combined with tunable parameters, enables the identification and validation of optimal growth patterns, supported by an algorithm designed to extract key features of hyphae–the fundamental building blocks of the mycelial network. Subsequently, the small-world properties of the modeled mycelium networks were investigated, revealing high clustering coefficients and short path lengths, characteristics that make them well-suited for reservoir computing (RC). To demonstrate their computational capabilities, mycelium-inspired RC architectures were evaluated on the MNIST dataset classification task, achieving an accuracy of up to 97.09%, highlighting the effectiveness of biologically inspired models. As a result, this framework establishes a comprehensive test-bench for mycelium modeling, growth, and computational exploration, paving the way for innovative applications in bio-inspired computing.

In the era of high-performance computing, the integration of Cellular Automata (CA) principles into low-power hardware is a challenging but intriguing endeavor. At the same time, memristors have gained attention due to their potential in in-memory neuromorphic computing. As such, the concept of Wave Cellular Automata (WCA) is presented a novel computing paradigm that leverages CA principles and memristive devices for in-memory computing. However, memristive devices are subject to variability effects, which can impact their performance and, in the case of WCAs, the generation of oscillations crucial for computation. This paper explores the variability tolerance analysis of WCA both in CBRAM device level, but also in its oscillatory behavior. The analysis reveals that WCA operation remains robust even in the presence of variability, with the impact on oscillation amplitude being minor. All in all, proper circuit design and element selection play a significant role in mitigating the effects of variability.

A swarm of miniature robots comprises mini-robots collaborating to achieve common goals, inspired by the collective behavior of insects. This concept mimics decentralized cooperation, enabling complex task accomplishment across various fields such as healthcare, exploration, and rescue missions. Mini-robots operate in confined spaces and time frames with minimal energy, requiring efficient path planning to prevent collisions within their group and surroundings. Integrating ultra-low-power electronics in these robots is essential. Memristors, renowned for their low power consumption, simplicity, and high integration density, hold significant promise. This paper proposes an integrated collision avoidance memristive circuit with neuromorphic behavior for miniature robots. This circuit not only enhances swarm efficiency but also lays the groundwork for fully analog mini-robots.

Abstract The use of Cellular Automata (CA) in combination with Learning Automata (LA) has demonstrated effectiveness in handling hard-to-be-solved problems. Due to their capacity to learn and adapt, as well as their inherent parallelism, they can expedite the problem-solving process for a range of problems, such as challenging logic puzzles. One such puzzle is Sudoku, which poses a combinatorial optimization challenge of great difficulty and complexity. In this study, a Sudoku puzzle was represented as an Irregular Learning Cellular Automaton (ILCA), using a reward and penalty algorithm to resolve it. Simulations for an amount of 400 puzzles were performed, while the results demonstrate that the proposed algorithm operates effectively, highlighting the concurrent and learning capabilities of the ILCA structure. Furthermore, two different performance enhancement methods are investigated, namely learning rates method and selective probability reset rule, which are able to increase the initial performance by $$26.8\%$$ 26.8 % and to achieve an overall $$99.3\%$$ 99.3 % resolution rate.

One of the most prominent examples of a complex system in nature is the nervous system, which exhibits oscil-lation phenomena across its structures, from single neurons to sophisticated neural networks. Memristors have been utilized in the past decade as a promising technology for building neuro-morphic systems due to their intrinsic neuromorphic properties. In this paper, we introduce a novel Memristor-based Oscillator (MBO) circuit design that implements both artificial neurons and artificial synapses in the same MBO-based medium, addressing scalability issues. The circuit design is transistor-free and simple, allowing high integration density. We utilize passive unipolar memristor devices based on the JART memristor model to design MBO neurons, which have been shown to reproduce bio-plausible spiking and bursting activities. Moreover, the MBO circuit is also realized as an artificial synapse incorporating synapse and axon mechanisms. Finally, the MBO neurons are modeled as Parkinson-related neuron types and their direct bidirectional coupling demonstrates that MBO neurons are effective in driving spiking activity in non-externally stimulated MBO neurons. This qualifies them for implementation in brain-inspired networks, providing low-cost Neurological-disease-related emulators.

The so far dominant Von Neumann architecture is being challenged by the energy demanding communication bottle-neck between processing and memory units. To address this issue, in-memory computing is employed for their co-location, with memristive crossbar arrays playing an important role towards this goal. Motivated by the above, this work introduces a timing-based programming of a memristor crossbar array for sequence generation in Stochastic Computing (SC). Its operation principle is based on the stochastic nature of the memristor devices forming the crossbar array, where their programming is regulated by the switching probability that follows the Poisson distribution, controlled by pulse amplitude and duration. The timing-based programming of the proposed crossbar array increases the discretization levels of the output probability values, thereby offering more accurate control when compared to programming schemes that consider only the pulse amplitude. The memristor's stochasticity along with the crossbar's inherent parallelism opens the in-memory design space allowing SC elements to be used as sequences are generated efficiently. Simulation results on different programming pulse-width precisions highlight the proposed crossbar's effectiveness in sequence generation, supported by mean absolute error (MAE) results in a standard SC arithmetic operation. Process variations stemming from the crossbar array affecting the sequence generation in SC are investigated.

The memristor crossbar architecture is a new technology that combines memory and computing on the same chip, finding numerous applications in modern bio-inspired computing systems. Recently, memristor-coupled Chua Circuit Networks (MCCNs) have been developed for the experimental confirmation of collective nonlinear phenomena, such as chimera states, that are also observed in the brain. For highly dense topologies, however, memristor crossbars can be prone to certain vulnerabilities. In this paper, we investigate the impact of sneak-path currents (SPCs) on the collective behaviors of chaotic oscillator networks, uncovering the network's tolerance to various realistic memristor crossbar designs. Despite the fact that these states alter the synchronization regime map, our findings suggest that SPCs have no detrimental impact on the formation and stability of single or multiple chimera states. This coupling issue along with other possible challenges are thoroughly discussed with a focus on nonlinear dynamics, highlighting the reliability of memristor crossbars as a coupling mechanism for studying chimera states.

Approximate computation has evolved recently as a viable alternative for maximizing energy efficiency. One aspect of approximate computing involves the design of hardware units that return a sufficiently accurate result for the examined occasion, rather than computing an accurate result. As long as the hardware units are allowed to compute approximately, they can be designed with multiple new ways. In this work, we focus on the synthesis of approximate parallel-prefix adders. Instead of exploring specific architectures, as done by state-of-the-art approaches, the introduced synthesizer can produce every solution that meets the designer’s criteria, resulting in adders with various delay, area, and error tradeoffs. This automatic design space exploration allows approaching, in several cases, optimal solutions that could have not been designed with any other known parallel-prefix architecture. The synthesized adders, when compared with state-of-the-art adders, achieve 27%–36% better error frequency (EF) on average for random inputs and improve image quality metrics by 8%–42% for image filtering. These results are achieved with the proposed adders requiring the same or marginally more hardware area or energy. On the contrary, in split-accuracy configurations, more than 30% of hardware area/energy can be saved for the same classification accuracy for a neural network application.

There is a continuous urge for higher efficiency in conventional computing systems, driven by an ever-growing demand for these systems’ complexity to be able to match the one of convoluted and challenging problems. However, this type of problems has formulated the benchmarks for unconventional computing systems to validate their emerging applicability and prove their effectiveness. Towards this path, Cellular Automata (CAs) have been established as a promising mathematical tool for simulating physical processes and demonstrated a favourable methodology for effectively implementing computations in hardware by taking advantage of their inherent parallelism. Representing CAs with oscillating memristive networks could further enhance the performance of these systems, by incorporating the rich dynamics evident in memristors and their strong memory and computing features. In this work, a wave generator circuit has been designed with low-voltage fabricated CBRAM devices, that is able to act as a Wave Cellular Automaton (WCA). These wave generation units are located on a grid with adjusting multi-directional interconnections between neighbors. In addition to that, the ability to reconFigure the amount of such units that influence each other, facilitates the propagation of voltage signals through the grid following wave propagation features. An example of this computational domain is presented with the realization of complex logic gates on the grid of WCAs.

The threshold switching effect is critical in memristor devices for a range of applications, from crossbar design reliability to simulating neuromorphic features using artificial neural networks. The rich inherit dynamics of a metallic conductive filament (CF) formation are thought to be linked to this characteristic. Simulating these dynamics is necessary to develop an accurate memristor model. In this work we present a compact memristor model that utilizes the drift, diffusion and thermo-diffusion effects. These three effects are taken into consideration to derive the switching behavior of a memristor. The resistance of a memristor is calculated based on the evolution of a truncated cone shaped filament. The objective of this model is to achieve a realistic integration of switching mechanisms of the memristor device, while minimizing the overhead on computing resources and being compatible with circuit design tools. The model incorporates the effect of thermo-diffusion on the switching pattern, providing a different perception of the ionic transport processes, which enable the unipolar switching. SPICE simulation results provide an exact match with experimental results of Metal-Insulator-Metal (MIM) memristive devices of Ag/Si2/SiO2.07/Pt nanoparticles (NPs) configuration.

The beneficial role of noise in the performance of Hf-based memristors has been experimentally studied. The addition of an external gaussian noise to the bias circuitry positively impacts the memristors characteristics by increasing the OFF/ON resistances ratio. The known stochastic resonance effect has been observed, when changing the standard deviation of the noise. The influence of the additive noise on the memristor current-voltage characteristic and on the set and reset related parameters are also presented.

The analysis of noise signals produced by semiconductor devices provides significant information for the origin and the physical mechanisms causing them, allowing for the mitigation of the noise sources, and improving the device performance. Furthermore, noise signals generated by RRAM and memristive devices can be utilized in cryptography security for applications due to their stochastic nature, revealing the positive effects of noise signals. In this work, the noise signals originated from metal-nitride-semiconductor memristive devices are investigated in terms of the influence of the wafer substrate used to fabricate them. Specifically, metal-insulator-semiconductor memristive devices on bulk Si and Silicon-On-Insulator substrates are examined. Parameter extraction and statistical analyses are performed assuming the typical models used for MOSFET devices. Preliminary results suggest that the measured noise signals originated from electron traps sited in the silicon nitride resistance switching layer. However, devices on SOI substrate generate lower noise signals compared to bulk devices, probably due to the better isolation of the active layer.

There is a growing interest in quantum computers and quantum algorithm development. It has been proved that ideal quantum computers, with zero error rates and large decoherence times, can solve problems that are intractable for today’s classical computers. Quantum computers use two resources, superposition and entanglement, that have no classical analog. Since quantum computer platforms that are currently available comprise only a few dozen of qubits, the use of quantum simulators is essential in developing and testing new quantum algorithms. We present a novel quantum simulator based on memristor crossbar circuits and use them to simulate well-known quantum algorithms, namely the Deutsch and Grover quantum algorithms. In quantum computing the dominant algebraic operations are matrix-vector multiplications. The execution time grows exponentially with the simulated number of qubits, causing an exponential slowdown in quantum algorithm execution using classical computers. In this work, we show that the inherent characteristics of memristor arrays can be used to overcome this problem and that memristor arrays can be used not only as independent quantum simulators but also as a part of a quantum computer stack where classical computers accelerators are connected. Our memristive crossbar circuits are re-configurable and can be programmed to simulate any quantum algorithm.

Synchronization transition in neuromorphic networks has attracted much attention recently as a fundamental property of biological neural networks, which relies on network connectivity along with different synaptic features. In this work, an area-optimized FPGA implementation of an Asynchronous Cellular Automata Neuron model that exhibits discrete-state neuron dynamics is introduced. The proposed neuron model is capable of reproducing various neuromorphic oscillations observed in biological neurons using less hardware resources than previous implementations. We investigate synchronization transitions with a focus on the emergence of chimera states in a ring-based network consisting of hardware-based neurons with electrical synaptic coupling. In particular, we study the effects on the network’s phase synchronization through changing two control parameters: the coupling range and the coupling strength. We indicate that via proper configuration of the coupling parameters, we influence the synchronization transition and reveal chimera states which have been associated with neurological disorders.

Nowadays we witness a miniaturisation trend in the semiconductor industry backed up by groundbreaking discoveries and designs in nanoscale characterisation and fabrication. To facilitate the trend and produce ever smaller, faster and cheaper computing devices, the size of nanoelectronic devices is now reaching the scale of atoms or molecules - a technical goal undoubtedly demanding for novel devices. Following the trend, we explore an unconventional route of implementing reservoir computing on a single protein molecule and introduce neuromorphic connectivity with a small-world networking property. We have chosen Izhikevich spiking neurons as elementary processors, corresponding to the atoms of verotoxin protein, and its molecule as a `hardware' architecture of the communication networks connecting the processors. We apply on a single readout layer, various training methods in a supervised fashion to investigate whether the molecular structured Reservoir Computing (RC) system is capable to deal with machine learning benchmarks. We start with the Remote Supervised Method, based on Spike-Timing-Dependent-Plasticity, and carry on with linear regression and scaled conjugate gradient back-propagation training methods. The RC network is evaluated as a proof-of-concept on the handwritten digit images from the standard MNIST and the extended MNIST datasets and demonstrates acceptable classification accuracies in comparison with other similar approaches.

Over the last years there has been significant progress in the development of quantum computers. It has been demonstrated that they can accelerate the solution of various problems exponentially compared to today's classical computers, harnessing the properties of superposition and entanglement, two resources that have no classical analog. Since quantum computer platforms that are currently available comprise only a few tenths of qubits, as well as the access to a fabricated quantum computer is time limited for the majority of researchers, the use of quantum simulators is essential in developing and testing new quantum algorithms. Taking inspiration from previous work on developing a novel quantum simulator based on memristor crossbar circuits, in this work, a framework that automates the circuit design of emulated quantum gates is presented. The proposed design framework deals with the generation and programming of memristor crossbar configuration that incorporates the desirable quantum circuit, leading to a technology agnostic design tool. To such a degree, various quantum gates can be efficiently emulated on memristor crossbar configurations for various types of memristive devices, aiming to assist and accelerate the fabrication process of a memristor based quantum simulator.

The time series of the brain are usually characterized by the co-existence of synchronized and desynchronized behaviors. This kind of behavior is related to normal and disorderly functions of the brain. One of the suggested mechanisms to understand thoroughly this behavior are chimera states, which are characterized by the coincidence of coherent and incoherent dynamics that can be exploited through networks of symmetrically coupled identical oscillators. In this work, ring-based networks of Chua's circuits, the simplest electronic oscillators that perform chaotic and well-known bifurcation phenomena, have been extensively studied in memristive crossbars (Xbar), revealing various collective spatio-temporal behaviors, such as chimera states. With respect to different Xbar connectivities and via SPICE-level circuit simulations, the proposed Xbar system proves its efficacy to reproduce spatio-temporal patterns spanning from complete synchronization and chimera states up to fully chaotic states.

Research progress in edge computing hardware, capable of demanding in-the-field processing tasks with simultaneous memory and low power properties, is leading the way towards a revolution in IoT hardware technology. Resistive random access memories (RRAM) are promising candidates for replacing current non-volatile memories and realize storage class memories, but also due to their memristive nature they are the perfect candidates for in-memory computing architectures. In this context, a CMOS compatible silicon nitride (SiN) device with memristive properties is presented accompanied by a data-fitted model extracted through analysis of measured resistance switching dynamics. Additionally, a new phototransistor-based image sensor architecture with integrated SiN memristor (1P1R) was presented. The in-memory computing capabilities of the 1P1R device were evaluated through SPICE-level circuit simulation with the previous presented device model. Finally, the fabrication aspects of the sensor are discussed.

The data transfer bottleneck in Von Neumann architecture owing to the separation between processor and memory hinders the development of high-performance computing. The computing in memory (CIM) concept is widely considered as a promising solution for overcoming this issue. In this article, we present a time-domain CIM (TD-CIM) scheme using spintronics, which can be applied to construct the energy-efficient convolutional neural network (CNN). Basic Boolean logic operations are implemented through recording the bit-line output at different moments. A multi-addend addition mechanism is then introduced based on the TD-CIM circuit, which can eliminate the cascaded full adders. To further optimize the compatibility of TD-CIM circuit for CNN, we also propose a quantization method that transforms floating-point parameters of pre-trained CNN models into fixed-point parameters. Finally, we build a TD-CIM architecture integrating with a highly reconfigurable array of field-free spin-orbit torque magnetic random access memory (SOT-MRAM) and evaluate its benefits for the quantized CNN. By performing digit recognition with the MNIST dataset, we find that the delay and energy are respectively reduced by 1.22.7 times and 2.4×103-1.1×104times compared with STT-CIM and CRAM based on spintronic memory. Finally, the recognition accuracy can reach 98.65% and 91.11% on MNIST and CIFAR10, respectively.

Memristor networks are capable of low-power and massive parallel processing and information storage. Moreover, they have presented the ability to apply for a vast number of intelligent data analysis applications targeting mobile edge devices and low power computing. Beyond the memory and conventional computing architectures, memristors are widely studied in circuits aiming for increased intelligence that are suitable to tackle complex problems in a power and area efficient manner, offering viable solutions oftenly arriving also from the biological principles of living organisms. In this paper, a memristive circuit exploiting the dynamics of oscillating networks is utilized for the resolution of very popular and NP-complete logic puzzles, like the well-known “Sudoku”. More specifically, the proposed circuit design methodology allows for appropriate usage of interconnections' advantages in a oscillation network and of memristor's switching dynamics resulting to logic-solvable puzzle-instances. The reduced complexity of the proposed circuit and its increased scalability constitute its main advantage against previous approaches and the broadly presented SPICE based simulations provide a clear proof of concept of the aforementioned appealing characteristics.

Multicast on-chip communication is encountered in various cache-coherence protocols targeting multi-core processors, and its pervasiveness is increasing due to the proliferation of machine learning accelerators. In-network handling of multicast traffic imposes additional switching-level restrictions to guarantee deadlock freedom, while it stresses the allocation efficiency of Network-on-Chip (NoC) routers. In this work, we propose a novel NoC router microarchitecture, called SmartFork, which employs a versatile and cost-efficient multicast packet replication scheme that allows the design of high-throughput and low-cost NoCs. The design is adapted to the average branch splitting observed in real-world multicast routing algorithms. Compared to state-of-the-art NoC multicast approaches, SmartFork is demonstrated to yield higher performance in terms of latency and throughput, while still offering a cost-effective implementation.

Machine learning adoption has seen a widespread bloom in recent years, with neural network implementations being at the forefront. In light of these developments, vector processors are currently experiencing a resurgence of interest, due to their inherent amenability to accelerate data-parallel algorithms required in machine learning environments. In this paper, we propose a scalable and high-performance RISC-V vector processor core. The presented processor employs a triptych of novel mechanisms that work synergistically to achieve the desired goals. An enhanced vector-specific incarnation of register renaming is proposed to facilitate dynamic hardware loop unrolling and alleviate instruction dependencies. Moreover, a cost-efficient decoupled execution scheme splits instructions into execution and memory-access streams, while hardware support for reductions accelerates the execution of key instructions in the RISC-V ISA. Extensive performance evaluation and hardware synthesis analysis validate the efficiency of the new architecture.

Resistive switching devices -memristors -present a tunable, incremental switching behavior. Tuning their state accurately, repeatedly and in a wide range, makes memristors well-suited for multi-level (ML) resistive memory cells and analog computing applications. In this brief, the tuning approach based on a memristor-resistor voltage divider (VD) is validated here experimentally using commercial memristors from Knowm Inc. and a custom circuit. Rapid and controllable multi-state SET tuning is shown with an appreciable range of different resistance values obtained as a function of the amplitude of the applied voltage pulse. The efficiency of the VD is finally compared against an adaptive pulse-based tuning protocol, in terms of circuit overhead, tuning precision, tuning time, and energy consumption, qualifying as a simple hardware solution for fast, reliable, and energy-efficient ML resistance tuning.

Since CMOS technology approaches its physical limits, the spotlight of computing technologies and architectures shifts to unconventional computing approaches. In this area, novel computing systems, inspired by natural and mostly nonelectronic approaches, provide also new ways of performing a wide range of computations, from simple logic gates to solving computationally hard problems. Reaction-diffusion processes constitute an information processing method, occurs in nature and are capable of massive parallel and low-power computing, such as chemical computing through Belousov-Zhabotinsky reaction. In this paper, inspired by these chemical processes and based on the wave-propagation information processing taking place in the reaction-diffusion media, the novel characteristics of the nanoelectronic element memristor are utilized to design innovative circuits of electronic excitable medium to perform both classical (Boolean) calculations and to model neuromorphic computations in the same Memristor-RLC (M-RLC) reconfigurable network.

Stochastic Resonance (SR) is a nonlinear system specific phenomenon, which was demonstrated to lead to system unexpected (counter-intuitive) performance improvements under certain noise conditions. Memristor, on the other hand, is a fundamentally nonlinear circuit element, thus susceptible to benefit from SR, which recently came in the spotlight of the emerging technologies potential candidates. However, at this time, the variability exhibited by manufactured memristor devices within the same array constitutes the main hurdle in the road towards the commercialisation of memristor-based memories and/or computing units. Thus, in this paper, memristor SR effects are explored, assuming various memristor models, and SR-based memristance range enhancement, tolerant to device-to-device variability, is demonstrated. Our experiments reveal that SR can induce significant RMAX/RMINratio increase under up to 60% variability, getting as high as 3.4× for 29 dBm noise power.

In this article, the problem of real-time robot exploration and map building (active SLAM) is considered. A single stereo vision camera is exploited by a fully autonomous robot to navigate, localize itself, define its surroundings, and avoid any possible obstacle in the aim of maximizing the mapped region following the optimal route. A modified version of the so-called cognitive-based adaptive optimization algorithm is introduced for the robot to successfully complete its tasks in real time and avoid any local minima entrapment. The method’s effectiveness and performance were tested under various simulation environments as well as real unknown areas with the use of properly equipped robots.

An accurate modelling of bio-electrochemical processes that govern Microbial Fuel Cells (MFCs) and mapping their behavior according to several parameters will enhance the development of MFC technology and enable their successful implementation in well defined applications. The geometry of the electrodes is among key parameters determining efficiency of MFCs due to the formation of a biofilm of anodophilic bacteria on the anode electrode, which is a decisive factor for the functionality of the device. We simulate the bio-electrochemical processes in an MFC while taking into account the geometry of the electrodes. Namely, lattice Boltzmann methods are used to simulate the fluid dynamics and the advection-diffusion phenomena in the anode compartment. The model is verified on voltage and current outputs of a single MFC derived from laboratory experiments under continuous flow. Conclusions can be obtained from a parametric analysis of the model concerning the design of the geometry of the anode compartment, the positioning and microstructure of the anode electrode, in order to achieve more efficient overall performance of the system. An example of such a parametric analysis is presented here, taking into account the positioning of the electrode in the anode compartment.

Cellular Automata (CA) is a nature-inspired and widespread computational model which is based on the collective and emergent parallel computing capability of units (cells) locally interconnected in an abstract brain-like structure. Each such unit, referred as CA cell, performs simplistic computations/processes. However, a network of such identical cells can exhibit nonlinear behavior and be used to model highly complex physical phenomena and processes and to solve problems that are highly complicated for conventional computers. Brain activity has always been considered one of the most complex physical processes and its modeling is of utter importance. This work combines the CA parallel computing capability with the nonlinear dynamics of the memristor, aiming to model brain activity during the epileptic seizures caused by the spreading of pathological dynamics from focal to healthy brain regions. A CA-based confrontation extended to include long-range interactions, combined with the recent notion of memristive electronics, is thus proposed as a modern and promising parallel approach to modeling of such complex physical phenomena. Simulation results show the efficiency of the proposed design and the appropriate reproduction of the spreading of an epileptic seizure.

Unconventional computing has been studied intensively, even after the appearance of CMOS technology. Currently, it has returned to the spotlight because CMOS is about to reach its physical limits, given that the constant demand for more computational power requires for novel unconventional computing solutions. In this area, the oscillatory internal motion mechanism of slime mould, namelyPhysarum Polycephalum, could serve as an alternative concept for the design and development of electronic circuits that exploit the memristive dynamics and simple LC contours to deliver solutions for computationally hard to be solved problems. In this direction, this work presents how bio-inspired memristive LC oscillators with a coupling capacitor can be synchronized to perform the functionalities of a biological neuron, also able to execute more complex computations, aiming to model biological neural systems much more advanced than the neuron-less slime mould biological organism. This work proposes a connection between the function mechanism of a simple biological organism and that of complex biological systems, made in a plausible and sufficient manner, towards unconventional computation with memristors.

This study deals with the evacuation of areas that involve people with disabilities. A crowd evacuation model has been developed using the Cellular Automata (CA) parallel computing tool. This model is capable of simulating and evaluating human behavior and special features that exist when people with disabilities are included in the process of evacuation. During the experimental process, the model simulates the evacuation of a secondary school for disabled children in the prefecture of Xanthi. After attendance and observation of an earthquake safety exercise organized by this school, the total evacuation time is recorded. At the end of this study, the developed model is validated on the basis of actual data and useful conclusions are drawn for the specific application area. In addition, with the modification of the original data, the model is applicable to every building case.

Summary The detection of ambiguous objects, although challenging, is of great importance for any surveillance system and especially for an unmanned aerial vehicle, where the measurements are affected by the great observing distance. Wildfire outbursts and illegal migration are only some of the examples that such a system should distinguish and report to the appropriate authorities. More specifically, Southern European countries commonly suffer from those problems due to the mountainous terrain and thick forests that contain. Unmanned aerial vehicles like the “Hellenic Civil Unmanned Air Vehicle” project have been designed to address high‐altitude detection tasks and patrol the borders and woodlands for any ambiguous activity. In this paper, a moment‐based blob detection approach is proposed that uses the thermal footprint obtained from single infrared images and distinguishes human‐ or fire‐sized and shaped figures. Our method is specifically designed so as to be appropriately integrated into hardware acceleration devices, such as General Purpose Computation on Graphics Processing Units (GPGPUs) and field programmable gate arrays, and takes full advantage of their respective parallelization capabilities succeeding real‐time performances and energy efficiency. The timing evaluation of the proposed hardware accelerated algorithm's adaptations shows an achieved speedup of up to 7 times, as compared to a highly optimized CPU‐only based version.

Special issue on high performance computing in modeling and simulationIn the pure technological era we are living, the need for appropriate tools, methods, and approaches that could boost and skyrocket real world various applications is of paramount importance even for daily life.Toward this direction, in the up-to-date literature, several computational tools are offered, new advanced nearly real-time performing techniques are introduced, almost every day, and powerful computing approaches are promising to tackle the issues of performance, energy efficiency, and computational burden, with many different fruitful ways.Nevertheless, most of these demands, trends, and perspectives would have never met the expected outcome without the help of modern high performance computing systems able to model and simulate computationally intensive scientific applications in the most efficient and appropriate way.Consequently, numerous and various high performance computing approaches like multi-/manycore systems, accelerators, compute clusters, and massively parallel machines, when combined with efficient numerical methods for differential equation systems and native computational paradigms, enable scientists and researchers worldwide to significantly advance the application of computing methodologies in research and industry applications, both in qualitative but mainly in quantitative way.In this aspect, this Special Issue aimed to offer both scientists and engineers in academy and industry an opportunity to express and discuss their views on current trends, challenges, and state-of-the art solutions to various problems in High Performance Computing for Modeling and Simulation.Moreover, it was highly related to the corresponding Special Session on High Performance Computing in Modeling and Simulation (HPCMS), within the 23rd Euromicro International Conference on Parallel, Distributed and network-based Processing (PDP), held in Turku, Finland on March 4-6, 2015, and its relevant topics.Eventually, a major part of these topics is covered by the content of the fore-coming Special Issue of Concurrency and Computation: Practice and Experience through eight (8) finally selected papers, all thoroughly reviewed and revised properly as a detailed major extension of their conference papers earlier published in the PDP 2015 proceedings.More specifically, in this Special Issue, both theoretical aspects of high performance computing systems, like libraries for the reduction of the programming burden of numerical models on heterogeneous parallel architectures, hybrid programming model MPI/OpenMP for tackling the communication load imbalance issues, and applications starting with parallel shared-memory version of the Space Saving algorithm for mining items, approximate and semi-asynchronous parallel model for supporting Parallel and Discrete Event Simulation, parallel execution pipeline of an existing description algorithm capable of characterizing both color and texture information of a given feature point for robotic visual place recognition, and parallel and hardware acceleration of detection of ambiguous objects for surveillance reasons, as well as optimization techniques to be parallelized such as Imperialist Competitive Algorithm, are fully considered in a fruitful and plausible way.In more details, the article by Chakroun et al 1 described ExaShark, 2 an open source library with the aim of reducing the programming burden of numerical models on heterogeneous parallel architectures.The presented library offers a global-array-like interface, whereas its run-time can be configured to use shared memory threading techniques, inter-node distribution techniques, or combinations of both.ExaShark takes advantage of the latest HPC technologies, helping to scale to future generation systems.The article demonstrates the usefulness of the ExaShark library through several experiments, including stencil codes, solvers, and matrix factorization algorithms.Utrera and co-authors 3 analyzed a significant problem in the field of HPC applied to modeling and simulation, that is, the communication load imbalance generated by irregular-data applications running in a multi-node cluster.The study targets, in particular, a hybrid programming model MPI+OpenMP, where several approaches to diminish communication load imbalance are adopted, like computation-communication overlap, issuing communications in parallel, and a new approach based on message fragmentation in order to take advantage of the eager-protocol.The article includes a number of interesting results of experiments, in which the performance of overlapped and non-overlapped approaches are quantified, including the impact due to network latency.The article by Majd et al 4 concerned another relevant aspect often involved in modeling and simulation, that is, optimization.In particular, the authors focus their work on parallelizing a relatively new evolutionary optimization approach, namely, the Imperialist Competitive Algorithm.5 The proposed parallelizations include a master-slave version and a more sophisticated multi-population strategy, both exploiting the well-known Message Passing Interface.The article describes a variety of experiments and comparisons, based on two different computing platforms, and proved that the developed parallel algorithms can achieve significant performances in both optimization and speed of execution.Rousset et al 6 presented nested graphs as an approach to model parallel and distributed multi-agent simulations aiming at facilitating the dynamic distribution of computations among parallel machines.The aforementioned task is successfully achieved due to finer granularity on multiple levels of abstraction.In the proposed approach, a common and generic framework, which represents the agent models, as well as their distribution, is efficiently presented.In addition, the proposed PDMAS framework includes a more graphical method to model parallel and distributed multi-agent

This paper presents a fully digital implementation of a memristor hardware (HW) simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field-programmable gate array families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks, implementing examples of associative memory and unsupervised learning of spatiotemporal correlations in parallel input streams using a simplified spike-timing-dependent plasticity. We provide the full circuit schematics of all our digital circuit designs and comment on the required HW resources and their scaling trends, thus presenting a design framework for applications based on our HW simulator.

This study presents the principles of a Cellular Automata (CA) based model that incorporates an enhanced version of the floor-field model targeting the fire spreading representation, thus called fire-floor-field (3F). The aim of the model is to simulate evacuation processes fast and reliably, in order to act as the core module of a near real-time effective anticipation system. To this direction, the model takes advantage of massive parallelism, an inherent feature of CA, by employing the efficient response of the floor field model and the accurate computational reproduction of fire-front evolution. Furthermore, a Graphic Processing Unit (GPU) based implementation of the proposed model is presented. Such a realisation aims at further speeding up the response of the model and it reinforces the fundamental goal of rapid activation. The model is validated quantitatively and qualitatively by being applied in the case of the two-dimensional (2D) simulated evacuation of the Building B, of the Department of Electrical and Computer Engineering, Democritus University of Thrace, under fire spreading conditions.

Quantum-dot fabrication and characterization is a well-established technology, which is used in photonics, quantum optics, and nanoelectronics. Four quantum-dots placed at the corners of a square form a unit cell, which can hold a bit of information and serve as a basis for quantum-dot cellular automata (QCA) nanoelectronic circuits. Although several basic QCA circuits have been designed, fabricated, and tested, proving that quantum-dots can form functional, fast and low-power nanoelectronic circuits, QCA nanoelectronics still remain at its infancy. One of the reasons for this is the lack of design automation tools, which will facilitate the systematic design of large QCA circuits that contemporary applications demand. Here we present novel, programmable QCA circuits, which are based on crossbar architecture. These circuits can be programmed to implement any Boolean function in analogy to CMOS field-programmable gate arrays and open the road that will lead to full design automation of QCA nanoelectronic circuits. Using this architecture we designed and simulated QCA circuits that proved to be area efficient, stable, and reliable.

This paper presents the principles of a Cellular Automata (CA) based model that focuses on assisted evacuation processes of elderly people and its parallel implementation. It is vital in venues that it is ensured punctual and safe evacuation of all people irrespective of their physical or mental condition. Obviously, in cases of emergency, such groups of people need special care in order to abandon an area. They themselves form a special category of moving people but they can be further subcategorized regarding their mobility capabilities, according to their different ailments (mobility disabilities, vision incapabilities, hearing weaknesses or even mental difficulties). The proposed model incorporates such parameters matching elderly people to different mobility groups that are assisted by specialized personnel. Multiple simulation scenarios have been performed that validate the response of the model qualitatively and quantitatively. Moreover, due to the inherent parallelism of CA, the solution of Graphic Processing Unit (GPU) is preferred to further speed up and proceed with the parallel implementation of the presented computational CA model. The aim of such a high performance computing implementation is to transform the proposed CA model to the basic module of an elderly crowd management anticipative system. Consequently, the model leads also to useful conclusions regarding proper venue layouts for efficient evacuation response.

Accumulated cost surfaces (ACSs) are a tool for spatial modelling used in a number of fields. Some relevant applications, especially in the areas of multi-criteria evaluation and spatial optimization, require the availability of several ACSs on the same raster, which may result in a significant computational cost. In this paper, we discuss some techniques available in the literature for accelerating the ACS computation using graphics processing units (GPUs) and CUDA. Also, we illustrate in details a new CUDA algorithm suitable for the computation of multiple ACSs. Moreover, we present some preliminary results on a test case, including an experimental comparison against a fast sequential implementation running on a CPU.

Resistive random access memory (ReRAM), referred to as memristor, is an emerging memory technology to potentially replace conventional memories, which will soon be facing serious design challenges related to continued scaling. Memristor-based crossbar architecture has been shown to be the best implementation for ReRAM. However, it faces a major challenge related to the sneak current (current sneak paths) flowing through unselected memory cells, which significantly reduces the voltage read margins. In this paper, five alternative architectures (topologies) are applied to minimize the impact of sneak current; the architectures are based on the introduction of insulating junctions within the crossbar. Simulations that were performed while considering different memory accessing aspects, such as bit reading versus word reading, stored data background distribution, crossbar dimensions, etc., showed that read margins can be increased significantly (up to 4×) as compared with standard crossbar architectures. In addition, the proposed architectures eliminate the requirement for extra select devices at each cross point and have no operational complexity overhead.

Within an ever-increasing variety of applications for memristors, adaptive electronic circuits have attracted considerable attention lately. This paper extends previously published work on memristive filter design to include the potential of composite memristive devices as damping elements in LC-based sensing circuits. The collective response of several LC contours with different memristive damping is considered. A thorough study of the circuit properties is performed in an attempt to exploit the high sensitivity of the circuit, other than address it as a typical drawback. The simulated circuits could find application in bio-inspired information processing, whereas could lead to better behavioral models for biological organisms.

Simulation is expected to become an indispensable educational and research tool for memristive circuits and architectures. To this end, this paper presents a novel, self-contained, platform-independent, GUI-based design and simulation tool for standard/alternative memristive crossbar architectures, targeting memory and/or logic applications. It permits the exploration of the crossbar-based memristive circuit design-space and allows for logic-in-memory computations.

This Live Demonstration is about an interactive software tool developed by the present authors. The tool will run on a personal laptop which the demonstrator will be responsible to bring to the conference site. There are no further special requirements and the mentioned provisions in the presentation booths, i.e. a power plug, a table, and a pin wall, are sufficient.

Illegal migration as well as wildfires constitute commonplace situations in southern European countries, where the mountainous terrain and thick forests make the surveillance and location of these incidents a tall task. This territory could benefit from Unmanned Aerial Vehicles (UAVs) equipped with optical and thermal sensors in conjunction with sophisticated image processing and computer vision algorithms, in order to detect suspicious activity or prevent the spreading of a fire. Taking into account that the flight height is about to two kilometers, human and fire detection algorithms are mainly based on blob detection. For both processes thermal imaging is used in order to improve the accuracy of the algorithms, while in the case of human recognition information like movement patterns as well as shadow size and shape are also considered. For fire detection a blob detector is utilized in conjunction with a color based descriptor, applied to thermal and optical images, respectively. Unlike fire, human detection is a more demanding process resulting in a more sophisticated and complex algorithm. The main difficulty of human detection originates from the high flight altitude. In images taken from high altitude where the ground sample distance is not small enough, people appear as small blobs occupying few pixels, leading corresponding research works to be based on blob detectors to detect humans. Their shadows as well as motion detection and object tracking can then be used to determine whether these regions of interest do depict humans. This work follows this motif as well, nevertheless, its main novelty lies in the fact that the human detection process is adapted for high altitude and vertical shooting images in contrast with the majority of other similar works where lower altitudes and different shooting angles are considered. Additionally, in the interest of making our algorithms as fast as possible in order for them to be used in real time during the UAV flights, parallel image processing with the help of a specialized hardware device based on Field Programmable Gate Array (FPGA) is being worked on.

The congregation of crowd undoubtedly constitutes an important risk factor, which may endanger the safety of the gathered people. The solution reported against this significant threat to citizens safety is to consider careful planning and measures. Thereupon, in this paper, we address the crowd evacuation problem by suggesting an innovative technological solution, namely, the use of mobile robot agents. The contribution of the proposed evacuation system is twofold: (i) it proposes an accurate Cellular Automaton simulation model capable of assessing the human behavior during emergency situations and (ii) it takes advantage of the simulation output to provide sufficient information to the mobile robotic guide, which in turn approaches and redirects a group of people towards a less congestive exit at a time. A custom-made mobile robotic platform was accordingly designed and developed. Last, the performance of the proposed robot guided evacuation model has been examined in real-world scenarios exhibiting significant performance improvement during the crucial first response time window.

Cellular automata (CAs) have been widely used to model and simulate physical systems and processes. CAs have also been successfully used as a VLSI architecture that proved to be very efficient at least in terms of silicon-area utilization and clock-speed maximization. Quantum cellular automata (QCAs) as one of the promising emerging technologies for nanoscale and quantum computing circuit implementation, provides very high scale integration, very high switching frequency and extremely low power characteristics. In this paper we present a new automated design architecture and a tool, namely DATICAQ (Design Automation Tool of 1-D CAs using QCAs), that builds a bridge between 1-D CAs as models of physical systems and processes and 1-D QCAs as nanoelectronic architecture. The QCA implementation of CAs not only drives the already developed CAs circuits to the nanoelectronics era but improves their performance significantly. The inputs of the proposed architecture are CA dimensionality, size, local rule, and initial and boundary conditions imposed by the particular problem. DATICAQ produces as output the layout of the QCA implementation of the particular 1-D CA model. Simulations of CA models for zero and periodic boundary conditions and the corresponding QCA circuits showed that the CA models have been successfully implemented.

Man-made transport networks and their design are closely related to the shortest path problem and considered amongst the most debated problems of computational intelligence. Apart from using conventional or bio-inspired computer algorithms, many researchers tried to solve this kind of problem using biological computing substrates, gas-discharge solvers, prototypes of a mobile droplet, and hot ice computers. In this aspect, another example of biological computer is the plasmodium of acellular slime mould Physarum polycephalum (P. polycephalum), which is a large single cell visible by an unaided eye and has been proven as a reliable living substrate for implementing biological computing devices for computational geometry, graph-theoretical problems, and optimization and imitation of transport networks. Although P. polycephalum is easy to experiment with, computing devices built with the living slime mould are extremely slow; it takes slime mould days to execute a computation. Consequently, mapping key computing mechanisms of the slime mould onto silicon would allow us to produce efficient bio-inspired computing devices to tackle with hard to solve computational intelligence problems like the aforementioned. Toward this direction, a cellular automaton (CA)-based, Physarum-inspired, network designing model is proposed. This novel CA-based model is inspired by the propagating strategy, the formation of tubular networks, and the computing abilities of the plasmodium of P. polycephalum. The results delivered by the CA model demonstrate a good match with several previously published results of experimental laboratory studies on imitation of man-made transport networks with P. polycephalum. Consequently, the proposed CA model can be used as a virtual, easy-to-access, and biomimicking laboratory emulator that will economize large time periods needed for biological experiments while producing networks almost identical to the tubular networks of the real-slime mould.

MapReduce is a widely used programming framework for the implementation of cloud computing application in data centers. This work presents a novel configurable hardware accelerator that is used to speed up the processing of multi-core and cloud computing applications based on the MapReduce programming framework. The proposed MapReduce configurable accelerator is augmented to multi-core processors and it performs a fast indexing and accumulation of the key/value pairs based on an efficient memory architecture using Cuckoo hashing. The MapReduce accelerator consists of the memory buffers that store the key/value pairs, and the processing units that are used to accumulate the key's value sent from the processors. In essence, this accelerator is used to alleviate the processors from executing the Reduce tasks, and thus executing only the Map tasks and emitting the intermediate key/value pairs to the hardware acceleration unit that performs the Reduce operation. The number and the size of the keys that can be stored on the accelerator are configurable and can be configured based on the application requirements. The MapReduce accelerator has been implemented and mapped to a multi-core FPGA with embedded ARM processors (Xilinx Zynq FPGA) and has been integrated with the MapReduce programming framework under Linux. The performance evaluation shows that the proposed accelerator can achieve up to 1.8x system speedup of the MapReduce applications and hence reduce significantly the execution time of multi-core and cloud computing applications. (Action: "Supporting Postdoctoral Researchers", "Education and Lifelong Learning" Program (GSRT) and co-financed by the ESF and the Greek State.)

In this paper we simulate the process of disembarking in a small airplane seat layout, based on Airbus A320/ Boeing 737, in search of ways to make it faster and safer under normal evacuation conditions, as well as emergency scenarios with the help of a model based on a parallel computational tool, namely Cellular Automata (CA). In specific, several case studies, including single and two opposite exits, different walking speeds of passengers depending on sex, age and height, the effect of retrieving and carrying luggage in addition to the presence of obstacles in the aisles, constituting a dynamic environment, as well as the emergence of panic are taken into account to enlighten the disembarking and emergency evacuation processes. The simulation results were compared to existing aircraft disembarking and evacuation times and indicate the efficacy of the proposed model to investigate and reveal the passenger attributes during these processes in all the examined cases. Finally, in order to speed up the simulation process and present a fully dynamical anticipative real-time system helpful for decision making we investigate the hardware implementation of the proposed here CA model in a Field Programmable Gate Array (FPGA) device.

Memories based on hysteretic resistive materials are expected to have superior properties such as nonvolatility, low power consumption, as well as very high capacity. Crossbar arrays are considered very attractive for future ultimately scaled memories. In this paper, the memristor-based passive crossbar geometry is studied and a set of different topological patterns, which introduce insulating junctions within the memory array, is presented. In the worst-case reading scenario the simulations revealed significantly improved sensed voltage margins (up to > 4×) which alleviate the rigorous requirement for large and highperformance CMOS sensing circuits in passive crossbar memory systems.

Power is becoming a critical constraint for designing embedded applications because the amount of power available to these portable systems is limited due to battery life. On the other hand, many of the emerging real-time applications designed for battery-operated systems, such as wireless communication, and audio and video processing, tend to compete in order to gain a larger fraction of the energy provided by the common (public) source. It is known that both cooperation and competition are very important for every vivid system operation and evolution because cooperation leads to the formation of more complex systems and competition is crucial for the efficient operation, especially when common sources are used. In this paper, we study the cooperation between individuals, i.e., power-aware jobs, of a group, i.e., an embedded system, in a power-aware changing environment, using a variation of the public goods game, in which the changing environment is modeled by a variable multiplication factor. Based on this PGG, we aim to find out what are the most essential conditions under which the cooperation between the power-aware jobs in periodically and abruptly power-aware changing environments of the embedded system is emerging and sustained. The most interesting result is that even in harsh situations, the jobs maintain a degree of cooperation to exploit favorable future energy changes in the power-aware environment.

In this paper, a hardware implementation of a fuzzy-modified ant colony processor that is suitable for image retrieval is presented for the first time. The proposed method utilizes three different descriptors in a two-stage fuzzy ant algorithm where the query image represents the nest and the database images represent the food. From the hardware point of view, only a small number of algorithms for hardware implementation have been reported in the image retrieval literature, since research focuses mainly on possible software solutions and the acceleration of existing algorithms. The proposed digital hardware structure is based on a sequence of pipeline stages, while parallel processing is also used in order to minimize computational times. It is capable of performing the extraction and comparison of features from (64$\,\times\,$64)-pixel-size color images, although through a simple transformation it can be easily expanded to accommodate images of larger sizes. The architecture of the processor is generic; the units that perform the fuzzy inference can be used with different descriptors than the ones proposed here and can be utilized for other fuzzy applications. It was designed, compiled, and simulated using the Quartus Programmable Logic Development System by the Altera Corporation. The fuzzy processor exhibits a level of inference performance of 800 K fuzzy logic inferences per second with 24 rules, and can be used for real-time applications where the need for short processing times is of the utmost importance.

The increasing complexity of computer networks calls for the development of new models for their simulation. Cellular automata (CAs) are a well-known and successful model for complex systems. This paper presents a system for modeling and simulation of computer networks based on CAs. More specifically, a 2D NaSch CA computer network model has been developed, and several networks were simulated. Algorithms for connectivity evaluation, system reliability evaluation, and shortest path computation in a computer network have also been implemented. Our system, called Net_CA system, was designed and developed as an interactive tool that offers automated modeling with the assistance of a dynamic and user-friendly graphical environment. The proposed system also produces automatically synthesizable very high speed integrated circuits hardware description language code leading to the parallel hardware implementation of the aformentioned CA algorithms. In terms of circuit design and layout, ease of mask generation, silicon area utilization, and maximization of achievable clock speed, CAs are perhaps the computational structures best suited for a fully parallel very large scale integrated realization. The simulation algorithms developed in the present paper offer high flexibility. Furthermore, connection reliability and other important parameters are inputs to the algorithms, rendering Net_CA a very reliable and fast simulator for wireless networks, ad hoc networks, and generally, for low connection reliability networks.

In this paper, a two-dimensional Cellular Automaton (CA) model simulates the evacuation process of a crowd responding to fire spread. The crowd consists of individuals and its behaviour is modelled by the response of each individual to a rule that directs him/her to the nearest exit. Furthermore, fire spreading and movements of the crowd members while approaching the fire are successfully simulated. Empirical studies and socio-psychological concepts that attempt to explain how individuals act under fire threat have been considered. Characteristic features of crowd dynamics, such as incoherent pedestrian motion, blockings in front of exits and mass behaviour are successfully simulated. An efficient user-friendly interface has been equipped with parameters defining the arrangement of the area, crowd formation and fire features. Finally, the model is executed fast on typical PCs and can be used for planning evacuation strategies under fire threat or as part of a real-time decision support system.

Nowadays, embedded consumer devices are expected to support demanding applications in terms of performance and energy consumption. For implementing such applications on Network- on-Chips (NoCs) a design methodology for performing exploration at system-level is needed, in order to select the optimal application-specific NoC architecture. In this paper we present a methodology for designing application-specific NoC platforms at system-level. The methodology is based on the exploration of different NoC aspects (e.g. topology, routing algorithms etc.) and is supported by a flexible NoC simulator. In this work we apply our methodology to applications modeled with Cellular Automata (CA).

In this paper, a one dimensional (1-d) cellular automaton (CA) for pseudorandom number generation (PRNG) and its reconfigurable hardware implementation are presented. The proposed 1-d CA based on the real time clock sequence (analytical time description) can generate high-quality random numbers which can pass all of the statistical tests of DIEHARD and NIST which seem to be the most powerfully complete general test suites for randomness. After describing our implementation in field-programmable gate array (FPGA), through experiments, we have identified the efficiency of the presented CA that performs exceptionally well compared to most known CA PRNGs reported in literature. More specifically, our CA implementation outperforms all the previous CA and LFSR PRNGs both in hardware implementation and timing characteristics. Such a CA can be efficiently implemented for PRNG reasons in every real time clock application with finally no silicon overhead.