Implementing last level caches (LLCs) with STT-MRAM is a promising approach for designing energy efficient microprocessors due to high density and low leakage power of its memory cells. However, peripheral circuits of an STT-MRAM cache still suffer from leakage power because large and leaky transistors are required to drive large write current to STT-MRAM element. To overcome this problem, we propose a new power management scheme called Immediate Sleep (IS). IS immediately turns off a subarray of an STT-MRAM cache if the next access is predicted to be not critical in performance. Thus, IS can effectively reduce leakage energy with little impact on performance. Our experimental results show that our technique can save the leakage energy of an STT-MRAM LLC by 32% compared to an STT-MRAM LLC with the conventional scheme at the same performance.

This paper presents novel processor architecture for HP-processor with nonvolatile/volatile hybrid cache memory. By simulations of high-performance (HP)-processor using MTJs, it has been clarified that total power of the HP-processor using perpendicular-(p-)STT-MRAM can be reduced by over 90 % with little degradation of processor performance. The presented architecture with nonvolatile memory hierarchy will realize the “normally-off computers”.

This paper describes a proposal of non-volatile cache architecture utilizing novel DRAM / MRAM cell-level hybrid structured memory (D-MRAM) that enables effective power reduction for high performance mobile SoCs without area overhead. Here, the key point to reduce active power is intermittent refresh process for the DRAM-mode. D-MRAM has advantage to reduce static power consumptions compared to the conventional SRAM, because there are no static leakage paths in the D-MRAM cell and it is not needed to supply voltage to its cells when used as the MRAM-mode. Besides, with advanced perpendicular magnetic tunnel junctions (p-MTJ), which decreases the write energy and latency without shortening its retention time, D-MRAM is capable of power reduction by replacing the traditional SRAM caches. Considering the 65-nm CMOS technology, the access latencies of 1MB memory macro are 2.2 ns / 1.5 ns for read / write in DRAM mode, and 2.2 ns / 4.5 ns in MRAM mode, while those of SRAM are 1.17 ns. The SPEC CPU2006 benchmarks have revealed that the energy per instruction (EPI) of the total cache memory can be dramatically reduced by 71 % on average, and the instruction per cycle (IPC) performance of the D-MRAM cache architecture degraded only by approximately 4 % on average in spite of its latency overhead.

Through silicon vias (TSVs) provide an efficient way to support vertical communication among different layers of a vertically stacked chip, enabling scalable 3-D networks-on-chip (NoC) architectures. Unfortunately, low TSV yields significantly impact the feasibility of high-bandwidth vertical connectivity. In this paper, we present a semi-automated design flow for 3-D NoCs including a defect-tolerance scheme to increase the global yield of 3-D stacked chips. Starting from an accurate physical and geometrical model of TSVs: 1) we extract a circuit-level model for vertical interconnections; 2) we use it to evaluate the design implications of extending switch architectures with ports in the vertical direction; moreover, 3) we present a defect-tolerance technique for TSV-based multi-bit links through an effective use of redundancy; and finally, 4) we present a design flow allowing for post-layout simulation of NoCs with links in all three physical dimensions. Experimental results show that a 3-D NoC implementation yields around 10% frequency improvement over a 2-D one, thanks to the propagation delay advantage of TSVs and the shorter links. In addition, the adopted fault tolerance scheme demonstrates a significant yield improvement, ranging from 66% to 98%, with a low area cost (20.9% on a vertical link in a NoC switch, which leads a modest 2.1% increase in the total switch area) in 130 nm technology, with minimal impact on very large-scale integrated design and test flows.

This paper describes ultra-low-power chip design using nano-scale electro-mechanical switches (NEMS) with graphene. This chip is attachable and detachable onto the top of other chips due to remarkable stickiness of carbon-nanotube interconnects. New 3D-IC can be thus constructed for reconfigurable system-on-chips. Furthermore, due to a floating gate built in NEMS, their logic performance is much superior to that of NEMS-based logic in previous works, and even better than that of conventional CMOS.

New FPGA deign using Dopant-Segregated Schottky MOSFET (DSS-MOSFET) and nonvolatile configuration memory (NCM) has been presented. Both of these devices can be fabricated by mature process for mass production. DSS-MOSFET has very low On-state resistance due to the high density dopant at source/drain junction. Therefore, FPGA is one of the best applications for the use of DSS-MOSFET since DSS-MOSFET can effectively improve not only CMOS logic performance but also pass-transistor logic performance. In addition, NCM with large On/Off resistance ratio, such as ionic memory, is adopted to replace SRAM-based configuration memory. Since NCM is fabricated between interconnect layers of CMOS, silicon area is smaller than in the case of SRAM. Furthermore, since NCM is a nonvolatile device, it is possible to reduce the power consumption by cutting off the power supply of unused circuit blocks. We developed a SPICE model of DSS-MOSFET to measure the delay of basic circuit in FPGA, and confirmed about 18% delay improvement for look-up-table with four to six inputs. We also designed physical layout to evaluate the area reduction of configuration memory, and verified the area of NCM is about 2.8X smaller than that of SRAM-based. Twenty largest MCNC benchmarks indicate that 26% improvement in critical path delay on average, and 15% improvement in area delay products on average can be achieved by the use of DSS-MOSFET and NCM.

Three-dimensional integrated circuits (3D-IC) have the potential to reduce interconnect length and improve performance especially in sub-65nm CMOS technologies. This paper describes design and performance analysis of the 3D-IC in sub-65nm CMOS technologies based on the accurate calculation of interconnects delays using 16-core processors as case studies. Performance improvement of the 3D-IC vs. 2D-IC is increased as CMOS scales down, which is consistent with the expected trend. The performance improvement is over 20%. Furthermore, performance of the 3D-IC in 65 nm (or 45 nm) CMOS technology is superior to that of the 2D-IC in 45 nm (or 32 nm) CMOS technology. It indicates that design conversion from 2D-IC to 3D-IC is superior to the CMOS technology migration according to COMS scaling. Reduction in repeater buffers and area overhead is also estimated.

During 1990s, silicon-based CMOS made steady advancement with miniaturization and with lower power consumption by incorporating the scaling effect and expanded its share by invading the region of bipolar transistors and compound semiconductors market. On the other hand, new semiconductor application technologies grew rapidly one after the other in conjunction with the development of silicone CMOS technologies. Such developments included the microprocessor for PC, server and router chipsets for internet application, RF for cellular phones, analogue circuitry, base band processors, and wireless LAN technologies. Also in memory areas, the flash memory technology was introduced into the market and FeRAM, MRAM, and PRAM technologies with new principles were introduced into the market.

No abstract available.

Recent progress of through-silicon-via (TSV) process is so impressive that everyone can expect real 3D-IC era. The most valuable advantages of 3D-IC is decreasing interconnects. Although analysis of this advantages has been reported in some specific case study, the general theory for quantitative analysis has not been studied. In some cases, the advantage of 3D-IC has been overestimated and much different from that of real chip designs expected. This paper presents the qualitative analysis of general 3D-IC design especially for sub-65nm CMOS generation from designers' point of view. What is understood from this paper is how important IC-design is for 3D-IC and how to gain a big advantage of 3D-IC.

Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Vias (TSVs) provide a promising area- and power-efficient way to support communication between different stack layers. Unfortunately, low TSV yield significantly impacts design of three-dimensional die stacks with a large number of TSVs. This paper presents a defect-tolerance technique for TSVs-based multi-bit links through an efficient and effective use of redundancy. This technique is ideally suited for three-dimensional network-on-chip (NoC) links. Simulation results demonstrate significant yield improvement, from 66% to 98%, with a low area cost (17% on a vertical link in a NoC switch, which leads a modest 2.1% increase the total switch area) in 130 nm technology, with minimal impact of VLSI design and test flows.

We present a ROM based logic design technique using reduced ROM size by eliminating identical rows and columns along with fast and low power single transistor cells. It substantially reduces the critical path length and thereby, improves the performance yet achieves low-power dissipation due to reduced number of switching. We present the ROM based design of a carry select adder (CSA) and two parallel prefix adders, which achieve more than 30% (in 32bit adder) delay reduction over their conventional designs at 90nm technology with as low as 9% (CSA) active power increase.

With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this article, we present a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasi-analytical model is effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide insight into how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit. We further show that unlike conventional MOSFET, nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and cylindrical gate geometry.

With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this paper, we propose a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasi-analytical model is seen to be effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.