In this article, we discuss the application of compiler technology for eliminating redundant computation in hardware simulation. We discuss how concurrency in hardware description languages (HDLs) presents opportunities for expression reuse across different threads. While accounting for discrete event simulation semantics, we extend the data flow analysis framework to concurrent threads. In this process, we introduce a rewriting scheme named ∂VF and a graph representation to model sensitivity relationships among threads. An algorithm for identifying common subexpressions as applied to HDLs is presented. Related issues, such as scheduling correctness, are also considered.

Abstract Single‐assignment and functional languages have value semantics that do not permit side‐effects. This lack of side‐effects makes automatic detection of parallelism and optimization for data locality in programs much easier. However, the same property poses a challenge in implementing these languages efficiently. This paper describes an optimizing compiler system that solves the key problem of aggregate copy elimination. The methods developed rely exclusively on compile‐time algorithms, including interprocedural analysis, that are applied to an intermediate data flow representation. By dividing the problem into update‐in‐place and build‐in‐place analysis, a small set of relatively simple techniques—edge substitution, graph pattern matching, substructure sharing and substructure targeting—was found to be very powerful. If combined properly and implemented carefully, the algorithms eliminate unnecessary copy operations to a very high degree. No run‐time overhead is imposed on the compiled programs.

Parser-based pattern matching proves to be attractive to compiler implementors because of its use in compiler-compilers. Semantic predicates can be added to parsers to augment the decision making power provided by syntactic analysis. This paper presents a practical technique to incorporate them within the framework of existing parser generators. A nearly vanilla parser can be used in this manner provided that epsilon productions are added to the grammar. Reduction by epsilon productions triggers the predicates, which as a side effect modify the lookahead symbol(s), thus influencing the progress of the parser at the last possible minute.

Abstract The problem of tracking data flow across procedure boundaries has a long history of theoretical study by people who believed that such information would be useful for code optimization. Building upon previous work, an algorithm for interprocedural data flow analysis has been implemented. The algorithm produces three flow‐insensitive summary sets: MOD, USE and ALIASES. The utility of the resulting information was investigated using an optimizing Pascal compiler. Over a sampling of 27 bench‐marks, new optimizations performed as a result of interprocedural summary information contributed almost nothing to program execution speed. Finally, related optimization techniques of possibly greater potential are discussed.

Compiler-component generators, such as lexical analyzer generators and parser generators, have long been used to facilitate the construction of compilers. A tree-manipulation language called twig has been developed to help construct efficient code generators. Twig transforms a tree-translation scheme into a code generator that combines a fast top-down tree-pattern matching algorithm with dynamic programming. Twig has been used to specify and construct code generators for several experimental compilers targeted for different machines.

We show that tree pattern matching has significant advantages in the specification and implementation of efficient code generators. We present a top-down tree-matching algorithm that is particularly well suited to code generation applications. Finally, we present a new back-end language that incorporates tree pattern matching with dynamic programming into a uniform framework for the specification and implementation of efficient code generators.

Affix grammars are used to describe the instruction set of a target architecture for purposes of compiler code generation. A code generator is obtained automatically for a compiler using attributed parsing techniques. A compiler built on this model can automatically perform most popular machine-dependent optimizations, including peephole optimizations. Code generators based on this model demonstrate retargetability for the VAX 1 -11, iAPX 2 -86, Z-8000 3 , PDP 4 -11, MC-68000, NS32032, FOM, and IBM-370 architectures.

Abstract This paper illustrates the usefulness of an attributed prefix linear intermediate representation for compiler code generation. In separating the machine‐independent and machine‐dependent aspects of a compiler, we discuss the advantages and disadvantages of an attributed linear intermediate representation with respect to tree‐structured intermediate representations. Some of these issues are relevant to fundamental questions of compiler structure with particular emphasis on retargetability. We discuss our implementation experience using this linear intermediate representation with a table‐driven code generation scheme for a variety of target architectures.

The instruction-set of a target architecture is represented as a set of attribute-grammar productions. A code generator is obtained automatically for any compiler using attributed parsing techniques. A compiler built on this model can automatically perform most popular machine-dependent optimizations, including peephole optimizations. The code generator is also easily retargetable to different machine architectures.