Logic Built-In Self-Test (LBIST) is becoming a requirement for high-complexity, high-reliability ICs which are increasingly used in the automotive field. Traditionally, LBIST can only be applied when there are no unknown simulation values (Xs) which would render the LBIST signature unusable. Eliminating all Xs in large industrial designs, especially when containing third party hard IP blocks, can be difficult, and anticipating all possible X-sources can be impractical. We present an X-tolerant LBIST solution (XLBIST) which uses compressor/decompressor structures, including X-control logic, that have already been inserted in the design for scan-compression deterministic patterns. Automatic test pattern generation (ATPG) leverages these structures to generate efficient XLBIST patterns. Patterns can be generated for any number (or density) of Xs, with resulting test coverage tradeoff. Results on industrial designs with high X densities demonstrate consistent XLBIST coverage.

As scan compression becomes ubiquitous, ever more complex designs require higher compression. This paper presents a novel, two-level compression system for scan input data generated by deterministic test generation. First, load care bits and X-control input data are encoded into PRPG seeds; next, seeds are selectively shared for further compression. The latter exploits the hierarchical nature of large designs with tens or hundreds of PRPGs. The system comprises a new architecture, which includes a simple instruction-decode unit, and new algorithms embedded into ATPG. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage and performance.

STIL consists of a series of standards under the IEEE 1450 label. Some of these efforts are approved, others in balloting, and others still being defined. This paper identifies the various efforts and discusses the motivations for the partitioning of these efforts. Industry concerns with this partitioning are presented, and an option to lower the barrier to acceptance for these efforts is identified

Logic built-in self test (BIST) is increasingly being adopted to improve test quality and reduce test costs for rapidly growing designs. Compared to deterministic automated test pattern generation (ATPG), BIST presents inherent fault diagnostic challenges. Previous diagnostic techniques have been limited in their diagnosis resolution and/or require significant hardware overhead. This paper proposes an interval-based scan-unload method that ensures diagnosis resolution down to gate-level faults with minimal hardware overhead. Tester fail-data collection is based on a novel construct incorporated into the design-extensions of the standard test-interface language (STIL). The implementation of the proposed method is presented and analyzed.

The relatively new Standard Test Interface Language (STIL) facilitates the transportation of digital test data from creation in computer-aided engineering (CAE) environments, to use on automated test equipment (ATE). Attempts to use STIL for this purpose have identified apparent disconnects in this flow. This paper presents disconnects identified to date, their causes, and presents solutions to address these issues. A practical example is presented of the process for transitioning an existing, known-good test flow to this new environment.

The Standard Test Interface Language (STIL) facilitates the transportation of digital test data from creation, to use on Automated Test Equipment. Constructs of the language, when used properly, support this operation. But these same constructs may also complicate the process. This paper discusses the appropriate use of STIL constructs for incremental test development, including an organizing paradigm for STIL data.

This paper presents the major features and capabilities of the new standard test interface language (STIL). A synopsis of the language, typical applications of the language, work that has been done to date, and degree of acceptance by the industry are discussed.

In an ideal world, all test vectors selected as I/sub DDQ/ test vectors would have very low measurement current. In many circumstances, however, a complete set of tests cannot be defined when relying on zero-current considerations. I/sub DDQ/ test vectors selected from existing test sets must be capable of compensating for passive currents. The identification of valid test vectors, and the magnitude of the passive current, can be predicted in the ASIC environment via macrocell-specific information. This paper presents one methodology to support this test generation using digital simulation, including the selection of multiple I/sub DDQ/ test vectors.

The author discusses the strong motivations for a standard test language. The capabilities of the Standard Test Interface Language (STIL) are examined and compared with other test standards which go too far into additional aspects of test.

This paper discusses practical issues in the generation of test data. Implementation requirements are derived from these issues, and a procedural test interface is described. A language to support that interface is presented, as well as methodologies to constrain an instance of the language to a particular tester.