In this paper, the WISQ architecture is described. This architecture is designed to achieve high performance by exploiting new compiler technology and using a highly segmented pipeline. By having a highly segmented pipeline, a very-high-speed clock can be used. Since a highly segmented pipeline will require relatively long pipelines, a way must be provided to minimize the effects of pipeline bubbles that are formed due to data and control dependencies. It is also important to provide a way of supporting precise interrupts. These goals are met, in part, by providing a reorder buffer to help restore the machine to a precise state. The architecture then makes the pipelining visible to the programmer/compiler by making the reorder buffer accessible and by explicitly providing that issued instructions cannot be affected by immediately preceding ones. Compiler techniques have been identified that can take advantage of the reorder buffer and permit a sustained execution rate approaching or exceeding one per clock. These techniques include using trace scheduling and providing a relatively easy way to “undo” instructions if the predicted branch path is not taken. We have also studied ways to further reduce the effects of branches by not having them executed in the execution unit. In particular, branches are detected and resolved in the instruction fetch unit. Using this approach, the execution unit is sent a stream of instructions (without branches) that are guaranteed to execute.

article Free Access Share on PIPE: a VLSI decoupled architecture Authors: J. R. Goodman The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Jian-tu Hsieh The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Koujuch Liou The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Andrew R. Pleszkun The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , P. B. Schechter The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Honesty C. Young The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 20–27https://doi.org/10.1145/327070.327117Published:01 June 1985Publication History 101citation592DownloadsMetricsTotal Citations101Total Downloads592Last 12 Months50Last 6 weeks13 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF