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José María López-Villegas

dblp:07/7266 · DBLP profile ↗
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8ranked-venue papers
0as first author
1since 2021 · last 2022
0000-0002-1333-7142ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 67% Integrated circuit design · 33%
Theoretical computer science
2 papers
Mathematical optimization · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
analog and RF circuit synthesis
0.932020
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Integrated circuit design
radio-frequency circuit design
0.522017
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Electronic design automation
design optimization
0.412020
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Electronic design automation
multi-objective optimization
0.412020
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Integrated circuit design › radio-frequency circuit design
low noise amplifier
0.312017
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Mathematical optimization
multi-objective optimization
0.122017
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014
Integrated circuit design › radio-frequency circuit design
radio frequency integrated circuits
0.112020
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2020
Mathematical optimization › multi-objective optimization
pareto front
0.112017
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017

Methods — techniques the papers use, named apart from their topics

multi-objective optimization · 1.4electromagnetic simulation · 1.4pareto-optimal front · 0.6electrical simulation · 0.4
YearPublicationVenuePosition
2022 Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission lines
abstract
This paper presents a 3D topology for high miniaturization of the well-known hybrid branch-line coupler at the UHF band. A preliminary work already proposed the use of helical-microstrip TLs combined with a folded structure for this purpose. This extended work includes a compactness enhancement by loading the TL segments with capacitors. An study of loaded helical-microstrip TL is reported as well. The coupler prototypes have been simulated and fabricated by using a combination of Additive Manufacturing and copper electroplating. The performance results have been compared to the conventional model showing a good agreement. In order to place the designed devices within the state of the art a figure of merit that combines the compactness and the relative bandwidth has been proposed, showing very good results in terms of miniaturization.
Arnau Salas Barenys, Neus Vidal, José María López-Villegas
Integr.3
2020 A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems
abstract
In recent years there has been a growing interest in electronic design automation methodologies for the optimization-based design of radio frequency (RF) circuits and systems. While for simple circuits several successful methodologies have been proposed, these very same methodologies exhibit significant deficiencies when the complexity of the circuit is increased. The majority of the published methodologies that can tackle RF systems are either based on high-level system specification tools or use models to estimate the system performances. Hence, such approaches do not usually provide the desired accuracy for RF systems. In this paper, a methodology based on hierarchical multilevel bottom-up design approaches is presented, where multiobjective optimization algorithms are used to design an entire RF system from the passive component level up to the system level. Furthermore, each level of the hierarchy is simulated with the highest accuracy possible: electromagnetic simulation accuracy at device-level and electrical simulations at circuit/system-level.
Fábio Passos, Elisenda Roca, Javier J. Sieiro, Rafaella Fiorelli, Rafael Castro-López, José María López-Villegas, Francisco V. Fernández 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.6
2018 Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator
Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández 0001
Integr.5
2017 An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors
abstract
A new design methodology for radiofrequency circuits is presented that includes electromagnetic (EM) simulation of the inductors into the optimization flow. This is achieved by previously generating the Pareto-optimal front (POF) of the inductors using EM simulation. Inductors are selected from the Pareto front and their S-parameter matrix is included in the circuit netlist that is simulated using an RF simulator. Generating the EM-simulated POF of inductors is computationally expensive, but once generated, it can be used for any circuit design. The methodology is illustrated both for a singleobjective and a multiobjective optimization of a low noise amplifier.
Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández 0001, Javier J. Sieiro, José María López-Villegas, Neus Vidal
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.6
2014 Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors
abstract
In this paper, a new methodology for the automated generation of the optimal performance trade-offs of integrated inductors is presented. The methodology combines a multiobjective optimization algorithm with electromagnetic simulation to get highly accurate results. A set of sized inductors is obtained showing the best performance trade-offs for a given technology. Unlike reported approaches for inductor synthesis, performance trade-offs are generated offline, i.e., before any specific inductance or quality factor are required. The tight efficiency versus accuracy trade-off of existing approaches is, in this way, avoided and performance evaluation via electromagnetic simulation becomes affordable.
Reinier Gonzalez-Echevarria, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández 0001, Javier J. Sieiro, Neus Vidal, José María López-Villegas
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.7
2010 Low-power current-reused RF front-end based on optimized transformers topology
Ignacio Gil, Ignasi Cairó, Javier J. Sieiro, José María López-Villegas
Integr.4
2010 Erratum to the Special Section on DCIS 2006 [Integration, the VLSI Journal, Volume 42, Issue 3, June 2009]
Manel Puig-Vidal, José María López-Villegas, Atila Herms
Integr.2
2009 CMOS single-ended-to-differential low-noise amplifier
Tomás Carrasco Carrillo, José Gabriel Macias-Montero, Aitor Osorio Martí, Javier J. Sieiro, José María López-Villegas
Integr.5