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Zongbin Liu

dblp:07/8064 · DBLP profile ↗
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26ranked-venue papers
3as first author
0since 2021 · last 2020
0000-0001-8117-0826ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Security and privacy · 22 · 2 first-authorSystems, architecture and hardware · 3 · 1 first-authorComputer networks · 1Software engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Cryptographic primitives and cryptanalysis · 80% Hardware security and side channels · 20%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic primitives and cryptanalysis › random number generation
entropy estimation
0.212014
Entropy Evaluation for Oscillator-Based True Random Number Generators · CHES 2014
Cryptographic primitives and cryptanalysis › random number generation › true random number generator
oscillator-based TRNG
0.212014
Entropy Evaluation for Oscillator-Based True Random Number Generators · CHES 2014
Cryptographic primitives and cryptanalysis
random number generation
0.212014
Entropy Evaluation for Oscillator-Based True Random Number Generators · CHES 2014
Hardware security and side channels › hardware security primitives
random number generator
0.212014
Entropy Evaluation for Oscillator-Based True Random Number Generators · CHES 2014
Cryptographic primitives and cryptanalysis › random number generation
true random number generator
0.212014
Entropy Evaluation for Oscillator-Based True Random Number Generators · CHES 2014

Methods — techniques the papers use, named apart from their topics

entropy evaluation · 0.2
YearPublicationVenuePosition
2020 Boosting Entropy Extraction of PDL-based RO PUF by High-order Difference Method
abstract
Ring Oscillator-based Physically Unclonable Function (RO PUF) is widely concerned because of its simple structure and good properties. Unfortunately, in order to maintain high reliability, the traditional RO PUF can only extract 1 bit entropy by comparing the frequency's magnitude of two selected ring oscillators (ROs), which is far from enough, especially in PUF-based key generation scenarios. In this paper, we propose an efficient and concise RO PUF response generation scheme based on FPGA platform by using high-order difference method, which significantly improves the response generation rate and entropy extraction rate of an RO pair by the fine control of Programmable Delay Lines (PDLs) in Look-Up Tables (LUTs). In addition, we build loop delay models and conduct extensive experiments on Xilinx's 28nm FPGAs (Kintex-7, Virtex-7 and Zynq-7000) to prove the effectiveness of our scheme.
Liang Zheng 0005, Changting Li, Zongbin Liu, Cunqing Ma
ACM Great Lakes Symposium on VLSI3
2020 Flush+Time: A High Accuracy and High Resolution Cache Attack On ARM-FPGA Embedded SoC
abstract
Flush based cache attacks have become a practical threat to data privacy and information security due to their advantages such as high accuracy and resolution. However, their accuracy and resolution still has room for improvement. In addition, although most of the attacks have been demonstrated on x86 processors, few of them have been executed on ARM devices. We propose a high accuracy, high resolution flush based cache attack, Flush+Time. This technique solves two important challenges for cache attacks on ARM: how to flush cache lines and how to achieve precise timing. Experiments show that Flush+Time increases accuracy from 95.1% of Flush+Reload, the most powerful general cache attack so far, to 99.3%. Flush+Time has a 30.5% higher resolution than Flush+Reload, but its execution time is only 0.59 times that of Spectre.
Churan Tang, Pengkun Liu, Cunqing Ma, Zongbin Liu, Jingquan Ge
VTS4
2019 A Low Overhead Error Correction Algorithm Using Random Permutation for SRAM PUFs
Liang Zheng 0005, Donglei Han, Zongbin Liu, Cunqing Ma, Lingchen Zhang, Churan Tang
ACISP3
2019 SecFlush: A Hardware/Software Collaborative Design for Real-Time Detection and Defense Against Flush-Based Cache Attacks
Churan Tang, Zongbin Liu, Cunqing Ma, Jingquan Ge, Chenyang Tu
ICICS2
2019 KPaM: A Key Protection Framework for Mobile Devices Based on Two-party Computation
abstract
Key protection on mobile devices is attracting more attention with the rapid growth of mobile payment. There are many key protection methods proposed in academia from the following three aspects. The first is from algorithmic perspective, such as white-box cryptography. The second is from physical protection perspective, such as secure element (SE). The last is from key escrow perspective, such as cloud secure element (Cloud SE). The security of the white box cryptography has not yet reached an agreement in academia, and SE cannot defend against unknown side channel attacks in the future since it can hardly be updated. With regard to Cloud SE, the user has to totally trust the cloud, including the cloud provider, the cloud environment, etc. However, with the development of attack methods, the complete credibility of the cloud has gradually become an excessive requirement. In this paper, we propose KPaM, a low-cost and flexible key protection framework for mobile devices, which can mitigate the issues described above. The main idea of KPaM is inspired by emerging two-party computation algorithm. The private key is split into two parts, stored and used in the mobile device and the cloud respectively. The cloud does not store the complete key, so there is no need to worry about the abuse of the user's private key. On the mobile side, we get rid of SE and use TEE (trusted execution environment) to perform cryptographic operations and access control mechanism, which realizes the functions of secure storage and trust path. At last, we take SM2 algorithm as an example to validate KPaM and evaluate its security and efficiency.
Zongbin Liu, Cunqing Ma, Lingchen Zhang, Donglei Han
ISCC2
2018 Implementation of High Throughput XTS-SM4 Module for Data Storage Devices
Liang Zheng 0005, Changting Li, Zongbin Liu, Lingchen Zhang, Cunqing Ma
SecureComm (2)3
2017 A Plausibly Deniable Encryption Scheme Utilizing PUF's Thermo-Sensitivity
Changting Li, Zongbin Liu, Lingchen Zhang, Cunqing Ma, Liang Zheng 0005
ICICS2
2017 A PUF and Software Collaborative Key Protection Scheme
Changting Li, Zongbin Liu, Lingchen Zhang, Cunqing Ma, Liang Zheng 0005
ICICS2
2016 HPAZ: A high-throughput pipeline architecture of ZUC in hardware
Zongbin Liu, Cunqing Ma, Changting Li, Jiwu Jing
DATE1
2016 Low-Cost Hardware Implementation of Elliptic Curve Cryptography for General Prime Fields
Zongbin Liu, Chenyang Tu, Jingqiang Lin 0001
ICICS3
2016 Novel MITM Attacks on Security Protocols in SDN: A Feasibility Study
Xin Wang 0086, Neng Gao, Lingchen Zhang, Zongbin Liu, Lei Wang 0135
ICICS4
2016 Detecting Side Channel Vulnerabilities in Improved Rotating S-Box Masking Scheme - Presenting Four Non-profiled Attacks
Zeyi Liu 0002, Neng Gao, Chenyang Tu, Zongbin Liu
SAC5
2016 FROPUF: How to Extract More Entropy from Two Ring Oscillators in FPGA-Based PUFs
Zongbin Liu, Cunqing Ma, Changting Li, Lingchen Zhang
SecureComm2
2015 QRL: A High Performance Quadruple-Rail Logic for Resisting DPA on FPGA Implementations
Chenyang Tu, Neng Gao, Zeyi Liu 0002, Zongbin Liu
ICICS6
2015 Bit Error Probability Evaluation of RO PUFs
Zongbin Liu, Cunqing Ma, Jiwu Jing
ISC2
2014 A High-Throughput Unrolled ZUC Core for 100Gbps Data Transmission
Zongbin Liu, Ji Xiang, Jiwu Jing
ACISP2
2014 Entropy Evaluation for Oscillator-Based True Random Number Generators
Jingqiang Lin 0001, Tianyu Chen 0016, Changwei Xu, Zongbin Liu, Jiwu Jing
CHES5
2014 TST: A New Randomness Test Method Based on Coupon Collector's Problem
Zongbin Liu, Quanwei Cai 0001, Ji Xiang
SecureComm (1)2
2013 A High-Speed Elliptic Curve Cryptographic Processor for Generic Curves over \mathrm p
Zongbin Liu, Wuqiong Pan, Jiwu Jing
Selected Areas in Cryptography2
2013 An Efficient Reconfigurable II-ONB Modular Multiplier
Liangsheng He, Tongjie Yang, Neng Gao, Zongbin Liu
SecureComm5
2012 Hardware Performance Optimization and Evaluation of SM3 Hash Algorithm on FPGA
Luning Xia, Jingqiang Lin 0001, Jiwu Jing, Zongbin Liu, Xingjie Yu
ICICS5
2012 Evaluating the Optimized Implementations of SNOW3G and ZUC on FPGA
abstract
SNOW 3G and ZUC are both the heart of secure algorithm sets in 3GPP LTE-Advanced, which is the potential candidate for 4G mobile broadband communication standard. In this paper, we optimize the implementation of the SNOW 3G and ZUC on FPGA, and also evaluate their performance. Our implementation of SNOW 3G reaches a little higher throughput than that of the best commercial IP core. Our optimized implementation of ZUC gives 40% performance improvement, compared with the best reported methods in terms of area-throughput ratio. Especially, compared with the ASIC implementation of ZUC in the most recent work in INDOCRYT 2011, the critical path of our architecture is 20% shorter than theirs. Our evaluation results show that both SNOW 3G and ZUC are flexible to balance different throughput with consumed area.
Lingchen Zhang, Luning Xia, Zongbin Liu, Jiwu Jing
TrustCom3
2011 An Efficient RSA Implementation without Precomputation
Wuqiong Pan, Jiwu Jing, Luning Xia, Zongbin Liu, Meng Yu 0001
Inscrypt4
2011 Evaluating Optimized Implementations of Stream Cipher ZUC Algorithm on FPGA
Lei Wang 0135, Jiwu Jing, Zongbin Liu, Lingchen Zhang, Wuqiong Pan
ICICS3
2011 A Tiny RSA Coprocessor based on Optimized Systolic Montgomery Architecture
Zongbin Liu, Luning Xia, Jiwu Jing, Peng Liu 0005
SECRYPT1
2010 Rate-Based Watermark Traceback: A New Approach
Zongbin Liu, Jiwu Jing, Peng Liu 0005
ISPEC1