The adoption of Commercial Off-The-Shelf (COTS) ICs in modern satellites faces challenges from radiation-induced latchup events, with current protection methods showing significant limitations in detection accuracy and applicability. This demonstration presents a novel adaptive AI-based latchup detection and protection system featuring two-stage training and LSTM neural network analysis. Our FPGA implementation achieves 90% detection accuracy without extensive pre-characterization. Visitors can validate the system's performance through real-time interaction with various latchup scenarios.

In our envisioned ‘Next Paradigm’ of ‘New Space’, commercial-off-the-shelf (COTS) systems (embodying multiple COTS ICs) would be employed as payloads in space missions. Most COTS ICs are susceptible to radiation effects, particularly Micro-Single-Event-Latchups (μ-SELs) and SELs, and their characteristics are expectedly different. Consequently, hitherto reported detection approaches require characterization of the individual COTS ICs and the entire system, thereby rendering excessive overheads when applied to different COTS systems. In this paper, we propose, for the first time, the design and implementation of an adaptive AI-based approach to detect and protect various uncharacterized COTS systems (vis-à-vis pre-characterized ones) against μ-SELs and SELs. Our proposal involves the adoption of the Long-Short-Term-Memory (LSTM) neural network with our proposed two-stage training process – ex-situ pre-training and in-situ re-training – to improve general applicability. Our FPGA-based prototype achieves high (~90%) average accuracy for four different payloads. This is a worthy improvement of 13.3%-28.5% over reported approaches, yet requiring low (~115 mW) power consumption. Collectively, our proposed approach is appropriate for resource-constrained space applications and our ‘Next Paradigm’ of ‘New Space’.

The average power-efficiency of integrated DC- DC converters for Internet-of-Things is generally compromised over a wide load current range. This is because their efficiency is typically severely compromised at light load currents. We present a novel asymmetrical segmented power-stage configuration to improve the average power-efficiency of integrated converters. We achieve this by configuring different power-stage segments with different sizes of power transistors and their inductors, and a circuit to enable the corresponding segment for high power-efficiencies at different load conditions. Specifically, the circuit enables the segment with small-sized power transistors and a large inductor for light-load operations, and conversely, it enables the segment with large-sized power transistors and a small inductor for heavy-load operations. The integrated converter employing our proposed configuration is designed using a CMOS 180 nm process for 2. 5-3.3V input, 1.2 V output, and 50 MHz switching frequency. Simulation results show the proposed converter achieves a high average power-efficiency at ~73% over a wide load current range of 5-200mA. When benchmarked against the competing contemporary designs, the proposed converter features 5-30% higher average power-efficiency over the wide load current range, and >34% higher power-efficiency at 20 mA light load.

Power-loss analyses for conventional (non fully-integrated) switched-mode dc-dc converters (SMCs) in the literature ignore the power losses due to the inductor and the gate driver of the power transistor. These losses are no longer negligible in fully-integrated SMCs. We propose closed-form expressions that characterize the aforesaid losses in fully-integrated buck SMCs. Using the expressions, we further analyze the overall power-efficiency, and show that designers can quickly find the combinations of design parameters that can achieve high power-efficiencies attainable by the SMC when realized using a target CMOS process.

We propose a novel high-rate low-power hybrid window analog-to-digital converter (HWADC) for monolithic digitally-controlled switched-mode dc-dc converters. Conventional Window ADCs are generally based on either voltage-controlled delay lines or ring oscillators. These ADCs usually have a small window size (input voltage range) and a low sampling rate (<;10 MHz) in order to reduce the required IC area and the power dissipation. The proposed HWADC employs a novel hybrid architecture that is a hybrid of delay-lines and ring-oscillators. The HWADC can achieve a large window size with a very high conversion rate, a small IC area, and low power dissipation. Further, the HWADC operates entirely based on digital logic, and is simple to realize using digital cells. The proposed HWADC is designed using a 65 nm CMOS process. Its IC area is 0.005 mm2. Simulation results at 1.2 V supply show that the HWADC can achieve a window size up to 1.2 V (configurable from 0.7 V to 1.9 V) at 250 MHz conversion rate and ~770 μW power dissipation. At the maximum window size of 1.2 V, the quantization step is 50 mV, or equivalently, a resolution of ~4.5 bits.

We propose a novel Variable-Delay Window ADC (VDWADC) design for digitally-controlled switched-mode dc-dc converters. In conventional Window ADCs based on the voltage-controlled delay line, the input voltage supplies the delay line. Thus, the conversion speed slows down when the input voltage decreases. The VDWADC is based on delay lines whose supply voltages are independent of the supply voltage. Hence, when the input voltage decreases, the conversion speed does not slow down. The VDWADC is simulated using 180 nm CMOS process and a supply voltage of 1.8 V. It achieves a quantization step of 0.05 V, or equivalently, a resolution of ~5.2 bits.

We present a fully-digital digital-to-analog converter (FD DAC) architecture design for high-speed communication systems. The FD DAC design is based on the ΔΣ modulation. The specifications for the DAC includes a low 1.2 V supply voltage, a high 5 GS/s input sampling rate, and a wide 2.5 GHz bandwidth. We employ a combination of the time-interleaving, parallel, and pipelining techniques to reduce the clock speed from 10 GHz to 625 MHz. The lower clock speed allows the use of standard cells for designing the digital computational circuits of the FD DAC. The critical building blocks of the FD DAC are laid-out in a 65 nm CMOS process. The post-layout simulation results show that the Signal to Noise and Distortion Ratio and the in-band Spurious-Free Dynamic Range of the output signal are 36 dB and 44 dBc respectively.

We propose a robust asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic (SAPTL) approach with improved speed and power attributes over reported SAPTL approach. These attributes are achieved by simplifying various sub-blocks therein to reduce the stacking of pass transistors and the number of transistor switchings, and to avoid floating nodes. By means of an 8-bit pipeline adder and on the basis of computation simulations (@ 1V, 45nm SOI process), we show that our proposed SAPTL adder is 37% faster, yet 14% lower power dissipation (@ 200MHz input-rate), 18% lower energy dissipation (per operation), and 47% better energy-delay product. These substantially improved attributes are achieved with insignificant overhead - just 3% more transistors.