Demo Data from EDBT 2026 / reviewers in the wild / expert
Maharaj Mukherjee
dblp:08/1068
· DBLP profile ↗
8ranked-venue papers
4as first author
0since 2021 · last 2008
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorComputer networks · 2Databases, data management, data science and information retrieval · 2 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 2 · 2 first-authorTheory of computation · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% | |
| Theoretical computer science
2 papers |
Computational complexity · 75% Computational geometry · 25% | |
| Computer graphics and multimedia
1 paper |
Geometric modeling and processing · 100% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.1 | 2 | 2008 | A Randomized Greedy Method for Rectangular-Pattern Fill Problems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Electronic design automation › physical design › layout density control
dummy fill insertion |
0.1 | 1 | 2008 | A Randomized Greedy Method for Rectangular-Pattern Fill Problems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Electronic design automation › physical design
floorplanning |
0.1 | 1 | 2008 | A Randomized Greedy Method for Rectangular-Pattern Fill Problems · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008 |
Electronic design automation › physical design
lithography |
0.1 | 1 | 2006 | Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Electronic design automation › physical design
optical proximity correction |
0.1 | 1 | 2006 | Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applications · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006 |
Geometric modeling and processing › computer-aided design › computer-aided geometric design
geometric constraints |
0.0 | 1 | 2000 | Satisfying coplanarity constraints on points sets in three dimensions with finite precision arithmetic · Comput. Aided Des. 2000 |
Computational geometry
finite precision arithmetic |
0.0 | 1 | 2000 | Satisfying coplanarity constraints on points sets in three dimensions with finite precision arithmetic · Comput. Aided Des. 2000 |
Methods — techniques the papers use, named apart from their topics
randomized greedy algorithm · 0.2simulated annealing · 0.1randomization · 0.1greedy algorithm · 0.1dynamic programming · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2008 | A Randomized Greedy Method for Rectangular-Pattern Fill ProblemsabstractIn this paper, a class of problems of physical-design optimization with rectangular shapes is presented. Efficient solutions for this class of optimization problems are needed for rectangular metal fill/negative-fill insertion during postrouting optimization. These problems are also shown to be closely related to the problem of floorplanning with rectangular macrocells. The solution must satisfy certain constraints for minimum and maximum pattern densities within a moving rectangular window while optimizing a given objective function such as the area or the aspect ratio of the resultant bounding box. It is shown in this paper that the general class of such problems defined with a gridless formulation is at least NP-hard. This proof, with minor modifications, also extends to the formulation in the gridded domain. A greedy randomized algorithm for one of our problems in the gridded domain is proposed, along with a proof that this algorithm can achieve the given objective with a very high probability while satisfying the constraints. Experimental results based on an implementation of our algorithm are provided and are shown to agree with our theoretical proof. Maharaj Mukherjee, Kanad Chakraborty |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2006 | Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applicationsabstractThe continuous drive of very large scale integrated (VLSI) chip manufacturers to meet Moore's law has spurred the development of novel resolution enhancement techniques (RETs) and optical proximity correction (OPC) methodologies in optical microlithography. These RET and OPC methods have increased the complexity of mask-manufacturing manifold and have, at the same time, put added emphasis on the mask inspection procedure. A technique to simplify mask inspection is to identify rectangular regions on the mask that do not require inspection. Such a region is referred to as a do not inspect region (DNIR). A novel and practical algorithm to place DNIR rectangles on the mask is presented. It is shown that the most general DNIR placement problem is at least NP-Hard (Garey and Johnson, 1979). However, under certain relaxed criteria, there exists a polynomial-time algorithm for DNIR placement using dynamic programming. However, the optimal algorithm has very-high-degree polynomial bounds on its runtime and space complexities. On the other hand, a very simple greedy algorithm extended by lookahead and randomization, or by simulated annealing, can greatly improve the performance of the DNIR placement and produce near-optimal results. Although the algorithm developed in this work is targeted primarily toward DNIR placement, it has many other VLSI design applications. Kanad Chakraborty, Alexey Lvov, Maharaj Mukherjee |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 2002 | A polynomial-time optimization algorithm for a rectilinear partitioning problem with applications in VLSI design automation
Maharaj Mukherjee, Kanad Chakraborty |
Inf. Process. Lett. | 1 |
| 2000 | Satisfying coplanarity constraints on points sets in three dimensions with finite precision arithmetic
Maharaj Mukherjee, A. R. Daherkar, R. Vattipalli |
Comput. Aided Des. | 1 |
| 1999 | An end-connected dual bus topology for metropolitan area networks
M. R. Ramapriya, S. Beotra, Maharaj Mukherjee, Ratnam V. Raja Kumar, P. Dhar |
Comput. Networks | 3 |
| 1997 | Design and Implementation of a Network Service Access Point (NSAP) for OSI-Compatibility
Abheek Saha, Maharaj Mukherjee, P. Dhar |
Comput. Networks ISDN Syst. | 2 |
| 1996 | A novel approach to represent 3-D isothetic scenes using XYZ treesabstractXYZ-tree is a hybrid data structure between object space and volume enumeration representation schemes. It is useful for isothetic polygons/polyhedrons and rectangles/rectangular parallelopipeds in 2/3-d. It is a compact and efficient data structure for representing city scape, VLSI circuits, printed circuit boards, etc. Trees may be combined using Boolean operators. Maharaj Mukherjee, Srinibas Vemuri |
ICIP (2) | 1 |
| 1991 | Constrained Integer Approximation to Planar Line Intersection
Shashank K. Mehta, Maharaj Mukherjee, George Nagy |
Inf. Process. Lett. | 2 |