As the transmission rates increase on the communication buses, the parasitic capacitance induced by large Electro-Static Discharge (ESD) protection devices raises challenges for normal operation of these buses. This is further challenging for high voltage systems like the Controller Area Network (CAN) bus used in automotive electronics. In order to meet the requirements of higher speed communication bus ESD protection, this paper showcases techniques for parasitic capacitance reduction without degrading the ESD performance of the clamp. The bidirectional floating base PNP clamp is designed for CAN bus in 0.13 μm foundry technology. Optimized structures are proposed to reduce the parasitic capacitance while maintaining the ESD robustness of the clamp. Up to 49% reduction on metal capacitance was achieved by rerouting the metal layers, and junction capacitance was reduced by lowering the doping concentration in the floating base and emitter finger. The measured capacitance show a reduction of up to 24% reduction in total capacitance while maintaining the same ESD performance.

Computational imaging concepts based on integrated edge AI and neural sensor concepts solve vision problems in an end-to-end, task-specific manner, by jointly optimizing the algorithmic and hardware parameters to sense data with high information value. They yield energy, data, and privacy efficient solutions, but rely on novel hardware concepts, yet to be scaled up. In this work, we present the first truly end-to-end trained imaging pipeline that optimizes imaging sensor parameters, available in standard CMOS design methods, jointly with the parameters of a given neural network on a specific task. Specifically, we derive an analytic, differentiable approach for the sensor layout parameterization that allows for task-specific, locally varying pixel resolutions. We present two pixel layout parameterization functions: rectangular and curvilinear grid shapes that retain a regular topology. We provide a drop-in module that approximates sensor simulation given existing high-resolution images to directly connect our method with existing deep learning models. We show for two different downstream tasks, classification and semantic segmentation, that network predictions benefit from learnable pixel layouts.

This paper presents a single stack structure integrating a Single Photon Avalanche Diode (SPAD) and a memristor, for rapid quenching and recharge using the short term memory of a memristor in its threshold switching behaviour. The fabricated device is compatible with typical CMOS process. It uses a circuit similar to passive quenching, typically used in single photon imaging devices. However, by using a memristor, it experimentally achieves performance similar to active reset operation without using additional circuitry and hence, at same pixel size and fill factor.

The high performance Neural Network accelerator architectures rely on either large external memory bandwidth and/or sparse computation paradigms which scale down unfavorably. Current state-of-the-art architectures also include on-chip SRAMs often more than 150 kB, establishing a lower bound on silicon area based on memory alone. This article presents an architecture which exploits programmable dataflow in combination with sparsity to make more efficient use of small on-chip memories. Its control logic supports an enlarged map space through uneven mappings, searched by a cost-model driven compiler to find points which allow prioritizing energy consumption and memory access over throughput. The problem of supporting sparse processing for flexible dataflows is circumvented by introducing an encoding scheme which provides sparsity metadata while still allowing random read and write access. Altogether, the system showcases enhanced performance in terms of external memory access while requiring only 51 kB of on-chip SRAM and small silicon area (0.5 mm2). The design achieves average energy efficiency of 4.4 TOPS/W and 9.7 inferences/s for a sparse AlexNet workload.

Using optical communications for smart dust applications enables small size of transceivers and offers a potentially large power advantage over RF. This paper presents an optically powered transceiver, which consists of on-chip solar cells, an optical receiver, a storage capacitor, and a passive transmitter formed by a liquid crystal (LC) modulator and a modulated retro-reflector (MRR). The transceiver circuit system has been fabricated using a standard 0.18-$ {\mu }\text{m}$CMOS process and the circuit area is$1 {\times }1.7$mm2excluding the MRR. Measurement results show that the complete transceiver can successfully work for 1-kb/s downlink and 10-b/s uplink under 0.5-V voltage supply and consume 53 nA totally. This indicates the transceiver can work at least in a 10-m range. It is successfully demonstrated that the transceiver scavenged the power from a 670-nm modulated laser beam sent by a base station (BS), extracted clock signal and the encoded data from the beam, decoded two designed instructions, switched theLCin the MRR and sent responses back to the BS. To the author’s best knowledge, this is the first time to present that an on-chip solar-cell powered transceiver realizes the two-way optical wireless communications for Internet of Things applications.

CMOS Image Sensors have a limited dynamic range. The need to increase the capability of imaging at a broad range of light intensities is of relevant interest in automotive and scientific applications. However, sensors that resolve the dynamic range issues, like logarithmic pixels, suffer from poor performance under low light conditions. This limitation is due to the inherent leakage current that flows through the photosensitive diode even in absence of light, and is hence referred to as dark current. The typical approaches to reduce this leakage current involve process modifications, which are costly, risky, time consuming and often not in the control of the designer. In this paper, a novel pixel design capable of reducing dark current without any process modifications is proposed. The pixel biases a diode at zero potential to reduce the leakage current. This pixel's architecture is based on a double current mirror to maintain the voltage drop on the photodiode as close to zero as possible. In addition, the pixel provides a logarithmic response, thereby capturing a wide dynamic range of intensities. Simulations results are reported showing that this architecture effectively achieves a small potential value on the photodiode.