Quality control in quantitative proteomics is a persistent challenge, particularly in identifying and managing outliers. Unsupervised learning models, which rely on data structure rather than predefined labels, offer potential solutions. However, without clear labels, their effectiveness might be compromised. Single models are susceptible to the randomness of parameters and initialization, which can result in a high rate of false positives. Ensemble models, on the other hand, have shown capabilities in effectively mitigating the impacts of such randomness and assisting in accurately detecting true outliers. Therefore, we introduced SEAOP, a Python toolbox that utilizes an ensemble mechanism by integrating multi-round data management and a statistics-based decision pipeline with multiple models. Specifically, SEAOP uses multi-round resampling to create diverse sub-data spaces and employs outlier detection methods to identify candidate outliers in each space. Candidates are then aggregated as confirmed outliers via a chi-square test, adhering to a 95% confidence level, to ensure the precision of the unsupervised approaches. Additionally, SEAOP introduces a visualization strategy, specifically designed to intuitively and effectively display the distribution of both outlier and non-outlier samples. Optimal hyperparameter models of SEAOP for outlier detection were identified by using a gradient-simulated standard dataset and Mann-Kendall trend test. The performance of the SEAOP toolbox was evaluated using three experimental datasets, confirming its reliability and accuracy in handling quantitative proteomics.

Polyp segmentation models have recently exhibited considerable success in computer-aided diagnostic systems. Despite the high performance demonstrated by numerous existing deep learning-based techniques on publicly available datasets, these methods still face challenges when it comes to accurate polyp recognition: (1) Undershoot and overshoot problems are frequent. (2) Robustness still needs to be improved in practical application scenarios. To tackle these challenges, we introduce a novel framework called Polyp2Former, which employs a decoupled mask feature strategy. Instead of optimizing the whole region, Polyp2Former divides the mask into the boundary and the body first and utilizes the boundary to refine the final result. It comprises three core components: the Query Embedding Module (QEM), the Mask Decoupling Module (MDM), and the Boundary Guided Module (BGM). These modules collectively contribute to achieving precise and resilient polyp segmentation. In QEM, the framework first embedded boundary and body information as input of MDM and BGM. In the MDM, we first warp the multiscale image features by learning a flow field to make the polyp more consistent, and the resulting body feature and the residual edge feature are further optimized under decoupled supervision by explicitly sampling different parts (polyp or boundary) pixels. In the BGM, we use the boundary map after mapping and the sigmoid function to guide the body feature to predict the final mask with better inner consistency and accurate boundary. Extensive experiments on four challenging polyp semantic segmentation benchmarks demonstrate that our proposed approach improves the segmentation accuracy and robustness significantly against the State-of-the-art methods through five-fold cross-validation and cross-datasets validation.

Underwater robots have been widely used in Marine environment monitoring, deep-sea resources exploration, underwater archaeology, and other fields. The underwater robot hovering is a very demanding technology, especially in a dynamic environment, the underwater multi-disturbance robot has a great influence, and accurate hovering of the underwater robot is the basic guarantee to complete the task. In this paper, a hybrid control strategy based on a neural network and PID is proposed to realize the perception and decision of complex environment states and realize the accurate hovering of the underwater robot. Experimental results show that the hybrid control based on neural network and PID can stably and accurately complete the hovering function, which proves the effectiveness of the algorithm. (Video: https://youtu.be/1GU4BKHeTB8t)

The precise positioning of underwater robots is the premise and foundation to complete other operations. Since a global positioning system (GPS) cannot be used underwater, and the positioning method of the underwater robot based on inertial navigation could cause significant errors, a multi-sensor information fusion method based on Elman neural network is proposed to solve these problems. The network is trained by taking data of doppler velocity log (DVL) and inertial measurement unit (IMU) as input and GPS as output. In the underwater area without GPS, the training network is used to predict the real-time position error of the acquired DVL and IMU data. The method can realize dynamic training and learning to improve the accuracy of the system. The experimental results show that the proposed method has lower positioning error than the traditional method, effectively inhibits the accumulation error of positioning, and improves underwater robots' positioning accuracy.

Interconnect optimization, including buffer insertion and Steiner tree construction, continues to be a pillar technology that largely determines overall chip performance. Buffer insertion algorithms in published literature are mostly focused on optimizing only the most critical path. This is a sensible approach for the first order effect. As people strive to squeeze out more performance in the post Moore's law era, the timing of near critical paths is worth considering as well. In this work, a p-norm based Figure Of Merit (pFOM) is proposed to account for both the critical and near critical path timing. Accordingly, a pFOM-driven buffer insertion method is developed. Further, the interaction with timing driven Steiner tree is investigated. The proposed techniques are validated in an industrial design flow and the results confirm their advantages.

Routing congestion has become a critical layout challenge in nanoscale circuits since it is a critical factor in determining the routability of a design. An unroutable design is not useful even though it closes on all other design metrics. Fast design closure can only be achieved by accurately evaluating whether a design is routable or not early in the design cycle. Lately, it has become common to use a “light mode” version of a global router to quickly evaluate the routability of a given placement. This approach suffers from three weaknesses: (i) it does not adequately model local routing resources, which can cause incorrect routability predictions that are only detected late, during detailed routing; (ii) the congestion maps obtained by it tend to have isolated hotspots surrounded by noncongested spots, called “noisy hotspots”, which further affects the accuracy in routability evaluation; and (iii) the metrics used to represent congestion may yield numbers that do not provide sufficient intuition to the designer, and moreover, they may often fail to predict the routability accurately. This article presents solutions to these issues. First, we propose three approaches to model local routing resources. Second, we propose a smoothing technique to reduce the number of noisy hotspots and obtain a more accurate routability evaluation result. Finally, we develop a new metric which represents congestion maps with higher fidelity. We apply the proposed techniques to several industrial circuits and demonstrate that one can better predict and evaluate design routability and that congestion mitigation tools can perform much better to improve the design routability.

To address the routability issue, routing congestion estimators (RCE) become essential in industrial design flow. Recently, several RCEs [1-4] based on global routing engines are developed, but they typically ignore the effects of routing on timing so that the identified routing paths may be overlong and thus impractical. To be aware of the timing issues, our proposed global-routing-based RCE obeys the layer directive and scenic constraints to respectively limit the routing layers and the maximum routing wirelength of the potentially timing-critical nets. To handle the scenic constrains, we propose a novel method based on a relaxation-legalization scheme. Also, because the work in [5] reveals that congestion ratio is a better indicator than overflow to evaluate routability, this work focuses on minimizing the congestion ratio rather than overflows. As will be shown, the problem of minimizing congestion ratio is more complicated than minimizing overflows, so we develop a new rip-up and rerouting scheme to reduce congestion and further to approach a target congestion ratio. Moreover, to fit the demands of practical uses, this work presents a control utility to trade off runtime and quality, which is an essential function to an industrial RCE tool. Experiments reveal that the proposed RCE is faster and more accurate than another industrial global-routing-based RCE.

For the last several technology generations, VLSI designs in new technology nodes have had to confront the challenges associated with reduced scaling in wire delays. The solution from industrial back-end-of-line process has been to add more and more thick metal layers to the wiring stacks. However, existing physical synthesis tools are usually not effective in handling these new thick layers for design closure. To fully leverage these degrees of freedom, it is essential for the design flow to provide better communication among the timer, the router, and different optimization engines. This work proposes a new algorithm, CATALYST, to perform congestion- and timing-aware layer directive assignment. Our flow balances routing resources among metal stacks so that designs benefit from the availability of thick metal layers by achieving improved timing and buffer usage reduction while maintaining routability. Experiments demonstrate the effectiveness of the proposed algorithm.

Existing routability-driven placers mostly employ rudimentary and often crude congestion models that fail to account for the complexities in modern designs, e.g., the impact of non-uniform wiring stacks, layer directives, partial and/or complete routing blockages, etc. In addition, they are hampered by congestion metrics that do not accurately score or represent design congestion. This is in large part due to the non-availability of public designs depicting industrial wiring stacks and other complexities affecting design routability.

Industry routers are very complex and time consuming, and are becoming more so with the explosion in design rules and design for manufacturability requirements that multiply with each technology node. Global routing is just the first phase of a router and serves the dual purpose of (i) seeding the following phases of a router and (ii) evaluating whether the current design point is routable. Lately, it has become common to use a "light mode" version of the global router, similar to today's academic routers, to quickly evaluate the routability of a given placement. This use model suffers from two primary weaknesses: (i) it does not adequately model the local routing resources, while the model is important to remove opens and shorts and eliminate DRC violations, (ii) the metrics used to represent congestion are non-intuitive and often fail to pinpoint the key issues that need to be addressed. This paper presents solutions to both issues, and empirically demonstrates that incorporating the proposed solutions within a global routing based congestion analyzer yields a more accurate view of design routability.

The impact of considering design hierarchy during physical synthesis remains a fairly under-researched area. This is especially true for large-scale circuit placement. This is in large part due to the non-availability of realistic public designs with the design hierarchy information. Additionally, modern designs are fairly complex with numerous placement blockages, non-uniform wiring stacks, partial and/or complete routing blockages, etc. This significantly complicates both, the placement and routing steps of physical synthesis.

At 65nm and below, Rapid Thermal Annealing (RTA) makes a significant contribution to manufacturing process variations, degrading the parametric yield. RTA-induced variability strongly depends on circuit layout patterns, particularly the distribution of the density of the Shallow Trench Isolation (STI) regions. In this work, we investigate a two-step approach to reduce the impact of RTA-induced variations. We first solve a floorplanning problem that aims to reduce the RTA variations by evening out the STI density distribution. Next, we insert dummy polysilicon fills to further improve the uniformity of the STI density. Experimental results show that our floorplanner can reduce the global RTA variations by 39% and the local variations by 29% on average with low overhead compared to a traditional floorplanner, and the proposed dummy fill algorithm can further reduce the RTA variations to negligible amounts. Moreover, when inserting dummy fills, for the layouts obtained by our floorplanner, on average, 24% fewer dummy polysilicon fills are inserted, as compared to the results from a traditional floorplanner.

This paper presents a router that minimizes the amount of dummy fill necessary to satisfy the requirements for chemical-mechanical polishing (CMP). The algorithm uses a greedy strategy and effective cost functions to control the maximal effective pattern density during routing. On a standard set of benchmark circuits, our CMP-aware router can reduce the required dummy fill by 22.0% on average, and up to 41.5%, as compared to the CMP-unaware case. In comparison with another CMP-aware routing approach, our algorithm is demonstrated to reduce the amount of dummy fill by 14.1% on average, and up to 23.6%, over the benchmarks.