Simple, accurate, portable, and selective gas sensors with autonomous, remote, and real-time access have become a requisite in various fields of applications. In this article, we report the development of a stand-alone and selective gas sensor system incorporating a single resistive sensor with wireless monitoring and Internet connectivity. The sensor is fabricated in-house with platinum-decorated tin-oxide hollow spheres as the sensing material, which exhibits a prominent response toward the tested volatile organic compounds (VOCs) at different concentrations. The intelligence in terms of accurate identification of VOCs and their concentration is attained by employing a machine learning tool based on a deep neural network. The applied model displays an average accuracy of 96.43% with a fast prediction speed of$310~\mu \text{s}$, allowing a real-time recognition capability. The wireless connectivity is established utilizing a low-power microcontroller board and a Bluetooth module. The real-time data is made available for the users over an Android-based mobile application and a webpage while utilizing cloud services through the Internet. The implemented system is successfully experimented with and validated under different test conditions that verify the whole platform. Further, the sensor system can be potentially applied to a remote application without needing any manual involvement. The demonstrated work with an Internet of Things (IoT) paradigm strengthens the next-generation gas sensing technology for developing smart, selective, and real-time gas sensor systems.

Wireless power delivery and telemetry have enabled completely implantable neural devices. Current day implants are controlled, monitored, and powered wirelessly, eliminating the need for batteries and prolonging the lifetime. A brief overview of wireless platforms for such implantable devices is presented in this paper alongside an in-depth discussion of wireless platform for peripheral nerve implants covering design requirements, link design, and safety. Initial acute studies on the performance of the wireless power and data links in rodents are also presented.

In this paper we present a novel approach for removing residual overlaps among blocks. We start out by representing the placement in the sequence pair form and describe transformations to the sequence pair to make the placement feasible. This is followed by a distance-based slack allocation to generate a new placement with no overlaps, while being as close to the original placement as possible. Our results demonstrate the efficacy of our approach in transforming layouts with overlaps to overlap-free layouts with minimal object movement.

Sequential place and route tools for field programmable gate arrays (FPGA's) are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty of accurately predicting wirability and delay during placement. A set of new performance-driven simultaneous placement/routing techniques has been developed for both row-based and island-style FPGA designs. These techniques rely on an iterative improvement placement algorithm augmented with fast, complete routing heuristics in the placement loop. For row-based designs, this new layout strategy yielded up to 28% improvements in timing and 33% in wirability for several MCNC benchmarks when compared to a traditional sequential place and route system in use at Texas Instruments. On a set of industrial designs for Xilinx 4000-series island-style FPGA's, our scheme produced 100% routed designs with 8-15% improvement in delay when compared to the Xilinx XACT5.0 place and route system.

The field programmable gate array (FPGA) routing resources are fixed and their usage is constrained by the location of programmable interconnects (PIs) such as antifuses. The routing or the interconnect delays are determined by the length of segments assigned to the nets of various lengths and the number of PIs programmed for routing of each net. Due to the use of PIs certain unconventional faults may appear. In this paper we model the PI faults and address the design and routability of the FPGA channel architecture to achieve 100% routing with minimum performance penalty in the presence of PI faults. A channel routing algorithm has also been developed which routes nets in the presence of PI faults. Experiments were performed by randomly injecting faults of different types into the routing channel and then using the routing algorithm to determine the routability of the synthesized architecture. Results on a set of industrial designs and MCNC benchmark examples show the feasibility of achieving routability with minimum performance penalty when a large number of faults are present in the channel.>

Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these at the placement level. A new performance-driven simultaneous placement / routing technique has been developed for row-based designs. Up to 28 % improvements in timing and 33 % in wirability have been achieved over a traditional sequential place and route system in use at Texas Instruments for several MCNC benchmark examples. 1

This paper introduces an automated transistor sizing tool (ASAP) that incorporates accurate gate-level functional models and can be used for delay, area, and power optimization of CMOS combinational logic circuits in a VLSI design environment. The optimization technique is based on simulated annealing and considers the performance improvement of VLSI circuits by optimally sizing the transistors on the N most critical paths.>

This paper considers automatic synthesis of segmented channel architecture of row-based FPGA's so as to achieve maximum routability and performance. The routability of a channel and the performance of the routed nets may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. For such a granular segmented channel architecture routing of long nets may require that several short segments be joined together by programming horizontal antifuses. Depending on the antifuse technology, the programmed antifuses can add considerably to the path delays. A channel architecture synthesis algorithm based on simulated annealing has been developed which enhances channel routability and performance. The synthesis algorithm is based on the fact that a strong correlation between the spatial distribution of nets and segments in a channel improves both routability and performance. Excellent results have been obtained for a set of benchmark examples and industrial designs.>

In FPGAs, routing resources are fixed and their usage is constrained by the location of antifuses. This severely limits the ability to make accurate wirability and timing predictions at the placement level. There is a need, therefore, for a layout flow in which an incremental placer changes the layout based on post-layout timing and wirability analysis. In this paper we consider such an incremental placer. Up to 29% improvement in timing has been obtained for a set of industrial designs and MCNC benchmark examples.

Considers routability and performance-driven optimization of a segmented channel architecture for row-based field programmable gate arrays (FPGAs). The routability of a channel and the performance of the routed circuit may have conflicting requirements. For a given number of tracks, very short segments usually enhance routability at the expense of performance. A simulated annealing-based channel segmentation optimization scheme has been developed, which enhances channel routability and performance based on the correlation between segment and net distributions. Excellent results have been obtained for a set of benchmark examples and industrial designs.>

Techniques for global and detailed routing of the macrocell-style analog core of a mixed-signal ASIC are discussed. A comparatively simple geometric model of the problem is combined with an aggressive simulated annealing formulation that selects paths while accommodating numerous signal-integrity constraints. Experimental results demonstrate that it is critical to attack such constraints both globally (system-level) and locally (channel-level) to meet designer-specified performance targets.>