A remote memory access poses a severe problem for the design of CC-NUMA multiprocessors because it takes an order of magnitude longer than the local memory access. The large latency arises partly due to the increased distance between the processor and remote memory over the interconnection network. In this paper, we develop a new switch architecture, called Switch MSHR (SMSHR), which provides the cache block to the requesting processors without those requests having to go to the home memory. The SMSHR idea is based on providing a few miss status holding registers (MSHRs) in each switch that keep track of read requests to the memory. The SMSHR blocks secondary requests to the same memory block and provides them with a copy of the block when the primary reply returns. The SMSHR design is then extended to include a switch cache, which can temporarily save a copy of the data block for later use. We provide basic block designs for the SMSHR and SIVISHR+cache architectures in this paper. We explore the design space by modeling the new switch architectures in a detailed execution-driven simulator and analyze the performance benefits. Our Simulation results show that applications with a high degree of data sharing benefit tremendously from the SMSHR and SMSHR+cache techniques.

A number of approaches have been proposed by different vendors for the next generation Internet router architectures, capable of processing millions of packets per second. Most of this processing speed stems from employing latest high-performance network processor or multiprocessors as the forwarding engine of the router However, all these improvements have been proposed without any detailed study in performance evaluation. The impact of instruction level parallelism, branch prediction, multiprocessing, and cache architectures on the performance of routers is not known. In the paper a methodology is proposed, which extends an execution-driven simulator to evaluate router architectures. We incorporate the exact model of an IP router into RSIM to analyze its performance and also develop a framework for feeding real Internet traces to the simulator Our work enables us to vary system parameters to simulate and analyze designs of realistic system with a range of traces. It is shown that the performance of Internet routers can be dramatically enhanced by using multiprocessor architectures. The router design also considers various cache replacement policies and router arbitration policies.

In this paper, the impact of memory management policies and switch design alternatives on the application performance of cache-coherent nonuniform memory access (CC-NUMA) multiprocessors is studied in detail. Memory management plays an important role in determining the performance of NUMA multiprocessors by dictating the placement of data among the distributed memory modules. We analyze memory traces of several scientific applications for three different memory management techniques, namely buddy, round-robin, and first-touch policies, and compare their memory system performance. Interconnection network switch designs that consider virtual channels and varying number of input buffers per switch are presented. Our performance evaluation is based on execution-driven simulation methodology to capture the dynamic changes in the network traffic during execution of the applications. It is shown that the use of cut-through switching with buffers and virtual channels can Improve the average message latency tremendously. However, the choice of memory management policy affects the amount of network traffic and the network access pattern. Thus, we vary the memory management policy and confirm the performance benefits of improved switch designs. Results of sensitivity studies by varying switch design parameters, cache block size, and memory page size are also presented. We find that a combination of first-touch memory management policy and a switch design with virtual channels and increased buffer space can reduce the average message latency by as high as 70 percent.

Bus-based systems are very attractive because they are simple and easy to use. This paper addresses the performance analysis of (N × N × B) prioritized bus-based multiprocessor systems. The interconnection networks considered include the complete multiple bus networks, the partial multiple bus networks and the partial multiple bus networks with K classes. The effective memory bandwidth is chosen as the performance measure. The proposed analytical models are derived under the assumption that a processor has a favourite memory module. The simulation experiments are performed. It can be shown that the results from theory models are very close to those from simulations.

This paper presents a cluster-based PPMB multiprocessor system and an analysis of its performance. The effective memory bandwidth is chosen as the main performance measure. Three situations are considered: (1) a processor is equally likely to address any one of the memory modules, (2) a processor has a few favorite memory modules, and (3) a processor has a few favorite and private memory modules. The results derived show that cluster-based PPMB multiprocessor system performs well and is fairly close to a typical processor-oriented partial multiple bus system for high rates of favorite requests. The number of connections of this system is also evaluated and compared with those of other systems. In addition, an improved model to determine the bandwidth of this system is presented under the assumption that the rejected memory requests are resubmitted in a memory cycle. It shows that the results obtained from this improved model match very closely those obtained from the simulation.