Human Activity Recognition poses a significant challenge within Active and Assisted Living (AAL) systems, relying extensively on ubiquitous environmental sensor-based acquisition devices to detect user situations in their daily living. Environmental measurement systems deployed indoors yield multiparametric data in heterogeneous formats, which presents a challenge for developing Machine Learning-based AAL models. We hypothesized that anomaly detection algorithms could be effectively employed to create data-driven models for monitoring home environments and that the complex multiparametric indoor measurements can often be represented by a relatively small number of latent variables generated through Manifold Learning (MnL) techniques. We examined both linear (Principal Component Analysis) and non-linear (AutoEncoders) techniques for generating these latent spaces and the utility of core domain detection techniques for identifying anomalies within the resulting low-dimensional manifolds. We benchmarked this approach using three publicly available datasets (hh105, Aruba, and Tulum) and one proprietary dataset (Elioth) for home environmental monitoring. Our results demonstrated the following key findings: (a) Nonlinear manifold estimation techniques offer significant advantages in retrieving latent variables when compared to linear techniques; (b) The quality of the reconstruction of the original multidimensional recordings serves as an acceptable indicator of the quality of the generated latent spaces; (c) Domain detection identifies regions of normality consistent with typical individual activities in these spaces; And (d) the system effectively detects deviations from typical activity patterns and labels anomalies. This study lays the groundwork for further exploration of enhanced methods for extracting information from MnL data models and their application within the AAL and possibly other sectors.

Recent and continuous technological advances in sensors, wireless communications and computing regarding price, size and power consumption have allowed the seamless integration of sensors into everyday objects in our homes and offices making non-intrusive user monitoring a reality. Intelligent processing of sensor data can be used to extract valuable information for carers so that they can provide better assistance to people such as elderly or disabled. These systems are commonly referred to as AAL (Ambient Assisted Living). In this paper we present an example of this approach called "Ambient Intelligence for Caregivers" or AmICare for short. Nodes of a WSN (Wireless Sensor Network) are integrated into furniture for non-intrusively monitoring of users' behaviour, whereas a software layer with an HMI (Human Machine Interface), that runs in a central node and server, can be configured with certain rules in a per resident basis to generate alerts to caregivers. AmICare is especially useful where there is need to supervise a high number of people (nursing homes, elderly or disabled people residences). A complete set of experimental tests has been carried out at a residence for intellectually disabled which requires massively distributed sensor nodes around all residence's bedrooms. This deployment in this scenario, the system architecture and its HMI are described in the paper. Finally, the testing procedure with the main significant results and caregivers' point of view are detailed.

A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. The main goal is to improve the applications execution time minimizing external memory transfers. Some amount of on-chip data storage is assumed to be available in the reconfigurable architecture. Therefore the Complete Data Scheduler tries to optimally exploit this storage, saving data and result transfers between on-chip and external memories. In order to do this, specific algorithms for data placement and replacement have been designed. We also show that a suitable data scheduling could decrease the number of transfers required to implement the dynamic reconfiguration of the system.

In this paper, we analyze the main issues in context scheduling for multicontext reconfigurable architectures from a formal point of view. We first provide an intuitive approach. which is later supported by a detailed analysis of the mathematical relations that express the reconfiguration process. This enables us to deduce a methodology for the minimization of context loading overhead, which considers the tradeoff between achievable system performance and algorithm efficiency. In this respect, the optimality necessary conditions are established in order to contrive an optimal search. However, as this approach is very time consuming we propose some heuristic techniques that reduce the algorithm complexity and accomplish very good results in relatively short execution time. This work has been developed as a part of an automated design environment for reconfigurable systems. A set of experiments has been developed so as to validate the theoretical results.

Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations.

In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications. This 2-million transistor design combines a reconfigurable array of cells with a RISC processor core and a high bandwidth memory interface. The system architecture, software tools including a scheduler for reconfigurable systems, and performance analysis (with impressive speedups) for target applications are described.

This paper describes a methodology to efficiently obtain a solution to the problem of context scheduling for multi-context reconfigurable architectures, regarding the minimization of context loading overhead. The target applications are assumed to be periodic, since it is a typical feature of many DSP and multimedia applications. This paper considers the trade-off between achievable system performance and algorithm efficiency. It has been developed as a part of an automated design environment for reconfigurable systems.

This paper describes a methodology to efficiently obtain a solution to the problem of context scheduling for multi-context reconfigurable architectures, regarding the minimization of context loading overhead. The target applications are assumed to be periodic, since it is a typical feature of many DSP and multimedia applications. This work considers the trade-off between achievable system performance and algorithm efficiency. It has been developed as a part of an automated design environment for reconfigurable systems.

Reconfigurable computing is a flexible way of facing with a single device a wide range of applications with a good level of performance. This area of computing involves different issues and concepts when compared with conventional computing systems. One of these concepts is context lending. The context refers to the coded configuration information to implement a particular circuit behaviour. An important problem for reconfigurable computing is the scheduling of a group of kernels (sub-tasks) that constitute a complex application for minimum execution time. In this paper, we show how the different execution orders for these sub-tasks may result in varying levels of performance. We formulate an analytical approach and present a solution for this new problem through this work.