This paper presents a novel approach to approximate logic synthesis (ALS) targeting at Dot-Inverter Graph (DIG), which is known for its superior expressive ability among all the 3-input gates and its potential in the future technology. We focus on minimizing the size of DIG circuits while maintaining acceptable error rates by introducing a Node Merging (NM)-enhanced Genetic Algorithm (GA)-based approach. The NM technique reduces the DIG size without altering its functionality, while the GA, incorporating Average Relative Hamming Distance (ARHD) and a self-adjusted mutation level, is used for ALS on DIGs. Our experimental results demonstrated that the proposed approach achieves a higher reduction rate and less CPU time on different sizes of circuits compared to the state-of-the-art ALS approach.

Identification of a Threshold Function (TF) is a significant task that determines whether a given Boolean function is a TF or not. The state-of-the-art only identifies all 8-input NP-class TFs. In this paper, we propose a new necessary condition for a function being a representative NP-class TF. With the proposed necessary condition, we design an effective approach to identify 9-input NP-class TFs. As a result, we reduce the candidate set of 9-input functions being TFs to an extremely tiny subset of all 9-input Boolean functions. Experimental results show that our approach successfully identifies at least 80% of 9-input NP-class TFs. This is the first attempt to deal with this challenging problem in the literature.

This paper presents a general methodology for designing optimal test structures and their applications to characterize the process fluctuations inherent in IC manufacturing. A set of test structures, including a novel test structure, is presented in which each test structure parameter is sensitive to a minimal number of process parameters. The procedure for device parameter extraction is described. Optimal device dimensions, criteria for choosing the sample sizes of test structures, and test chips are also determined based upon statistical hypothesis testing techniques. This methodology is illustrated by an application for tuning of the statistical process/device simulator FABRICS II to a typical NMOS fabrication process.

This paper presents a methodology for determining the probability of structural failures for VLSI circuits. An analytically based approach is used to perform simulations accurately and efficiently. This approach considers the specific IC layout and accounts for most of the fault mechanisms caused by global geometrical variations and local defects. A hierarchical model is proposed to describe the defect statistics including clustering. Strict analytical methods are used to find probabilities of failure for simple layout patterns. Then, the probability of failure for macrocells are calculated hierarchically. This methodology has been implemented in a CAD tool called RYE (Realistic Yield Evaluator). To demonstrate the effectiveness of this tool, the simulation results of several examples and the CPU time comparisons with Monte Carlo methods are also presented in this paper.