This paper examines parallel multiplier architectures with respect to post-layout energy and delay. Our energy-delay analysis applied to several schemes takes into account the architectural as well as practical circuit implementation issues. Incorporating extracted 3D parasitic loads after layout, our analysis leads to a more realistic conclusion than previous work. A novel parallel-select Booth2 coding method is proposed to improve the performance of the multiplier. Our analysis concludes that the Booth2 method achieves better energy efficiency for large multipliers and for high speed, while the non-Booth method consumes less for small multipliers and longer latencies.

We have developed a design flow from Verilog/VHDL to layout that mitigates the timing closure problem, while requiring no timing driven placement or routing tools. Timing issues are confined to the cell sizer, allowing the placement algorithm to focus solely on net lengths, resulting in superior layout densities and much lower power. The primary enablers to this new technology are: 1) gridded transistor sizing, 2) variable die routing that allows each net to be routed in the shortest possible length, 3) simultaneous cell placement, routing, gate sizing, and clock tree insertion, and 4) an effective incremental (ECO) placement that preserves net lengths from one iteration to the next. The variable die router is the key enabler. Superior placement and routing densities result from this new variable die approach. In addition, each net is routed at or near minimum length, and thus minor placement changes or cell size changes do not materially impact net lengths.