Demo Data from EDBT 2026 / reviewers in the wild / expert
Thomas F. Arnold
dblp:08/3066
· DBLP profile ↗
4ranked-venue papers
3as first author
0since 2021 · last 1973
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware reliability and fault tolerance · 42% Electronic design automation · 32% Storage systems · 21% | |
| Theoretical computer science
1 paper |
Automata and formal languages · 50% Computational complexity · 50% |
Topics — the 7 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Storage systems
data redundancy |
0.0 | 1 | 1973 | The Concept of Coverage and Its Effect on the Reliability Model of a Repairable System · IEEE Trans. Computers 1973 |
Hardware reliability and fault tolerance
reliability modeling |
0.0 | 1 | 1973 | The Concept of Coverage and Its Effect on the Reliability Model of a Repairable System · IEEE Trans. Computers 1973 |
Hardware reliability and fault tolerance › system reliability
repairable systems |
0.0 | 1 | 1973 | The Concept of Coverage and Its Effect on the Reliability Model of a Repairable System · IEEE Trans. Computers 1973 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1970 | Iteratively Realized Sequential Circuits · IEEE Trans. Computers 1970 |
Electronic design automation › logic synthesis
sequential circuit synthesis |
0.0 | 1 | 1970 | Iteratively Realized Sequential Circuits · IEEE Trans. Computers 1970 |
Automata and formal languages
pushdown automata |
0.0 | 1 | 1970 | R70-21 Time and Tape Complexity of Pushdown Automaton Languages · IEEE Trans. Computers 1970 |
Electronic design automation › logic synthesis
combinational logic synthesis |
0.0 | 1 | 1970 | Iteratively Realized Sequential Circuits · IEEE Trans. Computers 1970 |
Methods — techniques the papers use, named apart from their topics
reliability modeling · 0.0markov modeling · 0.0coverage analysis · 0.0pushdown store machine recognition · 0.0flow table realization · 0.0complexity analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1973 | The Concept of Coverage and Its Effect on the Reliability Model of a Repairable SystemabstractDuplication is a technique frequently employed to achieve high reliability for a repairable system. Although the philosophy of duplication is that it takes two faults to place a system out of service, there are generally some critical single faults that cause a system failure. This paper considers the effect of such a set of faults on a repairable system's reliability. It is shown that even a small number of such faults may severely degrade the mean time to system failure and the expected downtime for an otherwise highly reliable system. Thomas F. Arnold |
IEEE Trans. Computers | 1 |
| 1972 | Universal Modules for Bounded Signal Fan-Out Synchronous Sequential CircuitsabstractUniversal modules are presented that can be used to realize any single input-single output synchronous sequential machine in the form of a circuit in which the input signal enters only one module. Additionally, no signal in the circuit fans out to more than some bounded number of terminals where the bound depends only on the module being used. Two different realization schemes are presented. The first scheme is based on the single feedback loop circuit model. Modules are connected in a highly regular array. Inputs to the last row of the array are constant logic signals. In the second scheme, a tree of modules is connected at the back to one or more one-hot reaiizations of a machine closely related to the machine being realized. The first scheme has the advantage of yielding a circuit with a highly regular interconnections pattern. The second scheme generally requires fewer modules. The theory is easily edxtended to machines with more than one input and output. Monty Newborn, Thomas F. Arnold |
IEEE Trans. Computers | 2 |
| 1970 | R70-21 Time and Tape Complexity of Pushdown Automaton LanguagesabstractThis paper is concerned with the recognition of words which are contained in languages defined by pushdown store machines. Such languages exhibit many of the syntactic properties of algorithmic programming languages. Thus the recognition problem for languages generated by pushdown store machines is related to compilation of programming languages. Thomas F. Arnold |
IEEE Trans. Computers | 1 |
| 1970 | Iteratively Realized Sequential CircuitsabstractSynthesis techniques are presented for realizing an arbitrary synchronous flow table in the form of an array of identical modules interconnected in a regular pattern. Several types of structures and their corresponding modules are considered, and a relationship between these structures and earlier work on combinational circuits is shown. Thomas F. Arnold, Chung-Jen Tan, Monty Newborn |
IEEE Trans. Computers | 1 |