The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

The exponential growth in test data volume for modern Systems-on-Chip (SoCs), combined with a decreasing number of available test pins, has led to increased test time and complexity. Simultaneously, the industry’s drive for higher quality and lower Defective Parts Per Million (DPPM) necessitates continuous monitoring, testing, and repair Silicon Lifecycle Management (SLM). The advent of multi-die packaging technologies, such as 2.5D and 3D stacked integration, further exacerbates these challenges by introducing additional layers of interconnect and access constraints.Universal Chiplet Interconnect Express (UCIe) emerges as a compelling solution for delivering test content to all constituent dies at-speed, post-packaging. UCIe enables seamless test access across various lifecycle stages, including wafer sort, package test, System Level Test (SLT), and In-System Test (IST).This paper introduces a silicon-proven methodology that integrates the UCIe protocol with advanced SLM techniques to address the critical challenges of access, test, measurement and repair in complex multi-die SoC designs. Silicon results from test vehicles fabricated on TSMC N3P process with CoWoS-S packaging demonstrate complete interconnect, logic, and memory test, repair, and monitoring capabilities, validating the effectiveness and scalability of the proposed approach for next- - generation multi-die systems.

Aging of electronics can be caused by various physical mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB) and electromigration (EM). Aging phenomena may lead to a degradation of performance and reliability of an electronic system, hence limiting its expected lifetime. The goal of this paper is twofold. First, it presents an advanced, miniature design of an aging sensor; second, it shows how this sensor is integrated with a commercial 5 nm FinFET-based SRAM IP core. The sensor is implemented with a small number of logic gates, resulting in negligible overhead in area, power and delay. The sensor is also equipped with power gating capability. Thus, during idle time, the sensor is temporarily disconnected from the power supply lines to prevent aging of its transistors. Experimental results based on extensive SPICE simulations demonstrate that this approach is able to detect even the slight increase in memory response time due to aging much earlier than a functional error is observed at the memory output. This solution enables mission-mode monitoring of memory operation, which is a critical aspect of silicon lifecycle management (SLM) framework.

The long-term reliability of Static Random Access Memory (SRAM) is crucial for safety-critical applications, such as those in the automotive industry. In the front-end-of-line (FEoL), the transistor elements are susceptible to negative bias temperature instability (NBTI), while in the back-end-of-line (BEoL) the interconnects are susceptible to electromigration (EM), especially in scaled technology nodes. To meet safety-critical standards, it is essential to investigate the combined aging mechanisms within the SRAM array and to develop effective testing methodologies during the operational lifetime of the system. Such methodologies are also crucial for enabling the early detection of in-field failures. In this paper, a precise aging model is presented that extends the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model and includes physical modeling for EM. This approach provides insights into the combined effects of NBTI and EM on the degradation of SRAM writability, considering the entire SRAM subarray, including the bit-cell array and peripheral circuits in Fin Field-Effect Transistors (FinFET) technology.

The long-term reliability of the Static Random Access Memory (SRAM) module, as an important component of computing architectures, is crucial for safety-critical applications such as automotive. In the front end of the line (FEoL), the transistor elements are vulnerable to negative bias temperature instability (NBTI), while the back end of the line (BEoL) interconnect is prone to electromigration (EM). Complying with safety-critical standards as part of silicon lifecycle management (SLM) infrastructure requires an understanding of the combined aging mechanisms of transistors and interconnects in SRAM. Moreover, a precise aging model is a prerequisite for effective aging testing and mitigation strategies. For this aim, we augment the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model at the FEoL, and use measurement-calibrated physical modeling of EM at the BEoL, to create an integrated analysis that can provide deeper insights into the individual and combined effects of NBTI and EM for SRAM operation. Our findings reveal the mutual acceleration of delay faults and hard stuck-at faults caused by NBTI and EM in SRAM, offering a precise methodology for estimating the time to failure under these conditions.

Chip aging that results in small delay defects is one of the possible causes for silent data corruption that has been observed in large datacenters. Chip aging is exacerbated by high software workloads when the chip is deployed in a system. Small delay defects are detected by tests for path delay faults. Path delay faults are typically selected to include the longest testable paths. In addition, functionally possible paths are selected to ensure the detection of small delay defects that can cause a chip to fail during functional operation. To address chip aging, it is suggested in this brief that the longest functionally possible paths through as many lines as possible with the highest susceptibilities to aging should be targeted. A path selection procedure at the gate level is described, that uses the switching activity under functional test sequences to identify functionally possible paths that are the most susceptible to aging. Experimental results for benchmark circuits show that the length of a path and the functional switching activities for lines along the path are independent, and each criterion alone leads to the selection of different paths. The results suggest that both criteria need to be used together for path selection.

The advanced CMOS technology with smaller feature sizes has greatly improved the performance, energy, and area efficiency of the VLSI systems. Alongside the transistor feature size, back-end-of-the-line (BEoL) interconnects are also shrinking which makes them susceptible to electromigration (EM). Current density and temperature have decisive impacts on the EM profile of the BEoL interconnects, which themselves are highly affected by the running workload. Hence, the actual degradation and the remaining lifetime of a VLSI system are impacted by its usage scenarios. Therefore, in-field monitoring of the chip usage can predict failures before they happen and cause catastrophic failures, and in addition, provide an accurate estimate of the remaining useful lifetime to schedule preventive maintenance. In this work, we propose a simple yet effective on-chip EM sensor that can be embedded as a part of chip silicon lifecycle management (SLM) infrastructure. Further, we show how our proposed EM sensor can be effectively leveraged as a general sensor for the estimation of the remaining useful lifetime of the chip. The simulation results for the 5nm realistic SRAM design show that the power overhead of the proposed sensor is only 0.00365% of the SRAM module with a negligible area overhead.

Recent advances in automotive SOCs, artificial intelligence accelerators, and high-performance computing engines in data centers have led to an explosion in the adoption of emerging technology nodes and 3DIC/chiplet packages. This tutorial will present today’s trends and discuss on the resiliency challenges for such emerging SOCs. It will then focus on optimizing the SOC health using advanced solutions typically utilized for managing the different silicon lifecycle stages: from silicon debug in early bring up stage to shorten the time-to-volume; to self-test and repair during volume production stage, in order to improve quality and yield; to power-on self-test in the field stage to address aging challenges; to periodic checking in-system to improve functional safety; and finally to fault tolerance and error correction during mission mode to address a range of transient errors. All of the above optimizations are materialized by on-chip and/or off-chip data analytics.

With reliability being a critical factor in many applications today, in-system failure detection and correction is a key requirement for ensuring smooth operation in the field. For memory components that occupy the majority of the chip space, this is commonly accomplished with the help of error correcting codes (ECC). However, ECC can offer much more than plain error detection and correction. In particular, the paper describes some of the most common use cases of ECC that help not only to monitor memory health but also to extend its service lifetime by analyzing ECC data over time.

As the size and complexity of System-on-Chip (SoC) continue to grow, product performance and durability requirements have also become a vital part of chip design. By deploying monitors and structures built into the silicon design, we can obtain real-time data on the performance of the chip, which in turn can be used to study the health of the silicon and predict its degradation. This is a particularly important requirement for safety-critical applications such as automotive. In this paper, a case study of Path Margin Monitor (PMM) is presented as part of an automotive SoC subsystem that can monitor the functional paths of silicon in real-time throughout the entire silicon lifecycle.

The paper discusses the challenges that memory testing faces in the era of Gate-All-Around transistor technology and proposes a solution concept to overcome them. With the transition from two-dimensional to three-dimensional transistors, and in particular with the advent of FinFET, many new factors have entered the scene, creating a need for new testing techniques capable of coping with the complexity of novel memory designs. However, the end of the FinFET era and the beginning of a new Gate-All-Around design paradigm means that these methods need to be revisited to ensure they remain effective and in line with the latest transistor technologies that are contenders to replace FinFET. The paper assesses the test challenges associated with the Gate-All-Around technology and proposes a solution concept that sets a vector for a thorough investigation of underlying defects, fault modeling, and the development of efficient test and repair algorithms.

We need to address the multifaceted challenges about silicon and system quality throughout the life cycle of silicon-based systems, spanning from design, production to in-field deployment. Innovations spanning across various parts of the silicon ecosystem are needed. In this session we invited industry experts to discuss technical trends and challenges in semiconductor industry driving a pressing need of more innovations in the emerging field of silicon lifecycle management (SLM). They will present the state-of-the-art SLM methodologies and share their perspectives of this emerging field and thoughts of future R&D directions.

In today's complex applications, reliability is becoming an increasingly important issue, and one of the most attractive solutions for dealing with in-system failures is error correcting code (ECC). In this paper a novel protection technique is proposed based on an advanced ECC solution that takes into account the level of memory utilization and uses various ECC configurations to optimize power consumption, performance and area. The experimental results demonstrate the effectiveness of the proposed solution.

Safety is established as one of top priorities for Automotive SoCs along with security and reliability. However, testing is also known to play a crucial role since the degree of safety indirectly depends on the quality of test solution employed by SoC. In recent years, numerous studies and a large number of papers have been published on this topic, which seemed to form the necessary concepts and requirements for test solutions to achieve the desired level of functional safety. Among others, they introduced the concepts such as power-on self-test, check the checkers, mission mode test, periodic self-test, and so on. At this point, the question naturally arises whether we are hitting the limit, or we are still halfway there, and there is still room to improve field test and further enhance safety. During this session, we will ask speakers who are renowned experts in the field to share their views on the future of automotive industry and what comes next in terms of functional safety.

As automobiles become increasingly computerized, the safety requirement of hundreds of ICs used in a car is growing rapidly. Testing of such automotive ICs is more stringently than testing other ICs because the quality, reliability and functional safety of such ICs are extremely important as they are directly related to human lives. Many standards such as ISO 26262 are used to guide for high quality and long-term reliability driven by functional safety requirements. In this industry session, we invite 3 experts from IC design and EDA companies. They share their experiences with many case studies, and focus on different aspects of automotive testing, online monitoring, reliability and in-system functional safety.

This paper discusses the automotive requirements of ISO 26262 standard and its implication on conventional test and diagnosis flows. It presents a safety-oriented manufacturing test and diagnosis solution meeting automotive system-on-chip (SoC) requirements. The implementation details, automotive features and experimental results are described showing the effectiveness of the proposed solution.

This paper considers the reliability and safety issues in automotive applications which are of highest importance. FIT rate is one of the most common metrics used for quantitatively evaluating such issues. Strict requirements exist for acceptable FIT Rate in automotive applications. The problem of calculating the FIT rate at SoC level is considered in this paper and then it focuses on memories, which comprise a large part of current SoCs and have a great impact on the overall FIT rate. The vulnerability factors are considered, which help to get a better approximation of real-life situations. A methodology is presented for mitigating the effects of soft errors in memories via selective adoption of error detecting and correcting codes (ECC). Ways to calculate the FIT rate in the presence of ECC are considered and an advanced ECC solution is presented. Since using ECC increases the SoC area (extra logic and memory bits are needed) and decreases performance (delay in ECC logic that calculates / verifies the codes), a planning solution for choosing which memories should have ECC for optimal reliability/area is presented. Some experimental results are adduced to illustrate the effectiveness of the proposed techniques.

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This innovative practice session includes three presentations which discuss test and reliability issues and solutions for external and embedded memories. At speed test for external memories, memory array diagnosis and interconnect faults detection, as well as the peculiarities of supporting different memory IPs including DRAM and HBM2 are among the topics discussed. As for embedded memories, FIT rate calculation and mitigation methodology is presented which is shown to be critical for automotive SoCs.

This paper introduces a novel solution for building fault aware memory built-in self-test infrastructure based on rules of fault periodicity and regularity in memories and test algorithms. These periodicity and regularity rules are described via special internal structures named fault periodicity table (FPT) and test algorithm template (TAT). Three dimensions of evolution are considered as inputs for forming the mentioned structures: memory cells, multidimensional memory circuits, and memory systems for systems-on-chip where memories are distributed in different subchips. Each column of FPT corresponds to a fault nature which can be associated with a variety of different test mechanisms while each row of FPT corresponds to a fault family determined by the complexity of fault sensitization. FPT allows considering any large number of faults in one table while TAT allows constructing test algorithms without using test algorithm generation tools. Experimental results of the solution applied to both Planar-based (90/65/45/28 nm) and FinFET-based (16/10/7 nm) memory technologies are adduced also in this paper.

Automotive innovation is driving the need for built-in reliability, safety and security solutions and architectural design to mitigate emerging threats and, particularly, the number of possible sources affecting arisen failures. In other words, the problem can be stated as reduction of failure rate-one of the most common metrics used for reliability evaluation. Soft errors in memories will be considered in the paper. Their FIT rate is significantly more than the typical FIT rate for a hard reliability failure. A special technique is described to assess the soft error rate and to mitigate the effects of soft errors via error correcting codes (ECC). Ways to calculate the failure rate in the presence of ECC are considered jointly with different ECC solutions. Since ECC also incurs a significant area overhead, a problem arises how to choose memories in SoC which should have ECC in order to meet the reliability requirements and, at the same time, the area constraints. In this paper, an efficient ECC planning solution is presented to solve the problem. The experimental results are adduced which show the advantages of the proposed solution.

The fast growing Automotive SoC market presents new test challenges, combining traditional production requirements as well as new Functional Safety (FuSa) related aspects. In order to meet these challenges, an innovative approach must be introduced. This paper presents a detailed case study demonstrating typical Automotive SoC requirements, in addition to an advanced Uniformed Test Approach, specially tailored in order to fulfill them.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative technology for on-chip memories due to several advantages such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Due to the emerging fabrication processes of magnetic layers in the fabrication of STTMRAM devices, they are more susceptible to manufacturing defects and have different failure mechanisms compared to conventional CMOS memories. This mandates specific fault modeling and development of proper test algorithms for high coverage testing of these memories in order to ensure correct functionality in the field. In this paper, a detailed defect injection is performed based on the magnetic devices and layout characteristics of STT-MRAM and unique fault models are constructed for these memories. Based on the derived fault models and behaviors, efficient test algorithms are developed to fully cover these faults.

Automotive has become one of the most prevailing sectors of the modern semiconductor industry. Due to strict requirements for safety, reliability, and security the proposed test & repair solutions for automotive applications undergo a circumstantial verification before exploitation. Traditionally production defects and soft errors occurring in the operation mode were considered to be the main source of failures for System-on-Chips (SoC). Nevertheless, aging-induced faults especially in modern technology nodes also pose certain challenges for SoC lifetime and impact the overall Failure in Time (FIT) rate of the system. Meanwhile keeping hold of low FIT rate is one of the main criteria for reliability. In this paper, a comprehensive study on aging faults is conducted for FinFET memories and an efficient test & repair methodology is proposed that meets the automotive requirements and allows decreasing the FIT rate of the system.

The following topics are dealt with: integrated circuit testing; logic testing; automatic test pattern generation; integrated circuit design; integrated circuit manufacture; logic design; system-on-chip; fault diagnosis; integrated circuit reliability; automatic test equipment.

With increasing use of electronic systems in vehicles for managing critical functionality, the requirements for safety in automotive chip architectures are becoming mandatory. Thus, automotive chips must provide functional safety capabilities in addition to the general functionality. Augmenting logic and memory BIST (Built-in Self-Test) solutions with new features is one of the options to facilitate safety at chip level. The augmented solution self-test the logic and memory at power-up/power-down and during mission mode to ensure that the chip is fault-free or react if it is faulty. In this paper, an effective infrastructure is presented which allow detection of faults for functional safety.

The modern automotive industry has entered an era where the tendencies are towards increased automation and connectivity. With every new generation, the proportion of electronics-controlled systems in the vehicles is steadily growing. In parallel the safety and reliability requirements to automobiles are becoming more stringent thus requiring more sophisticated approaches. The problem is complicated by the fact that automotive has started to use cutting-edge technologies whose maturity might not be always at high level. Thus, there is a need to ensure not only low DPPM during production mode but also high reliability during mission mode. This paper presents an advanced Error Correcting Codes (ECC) solution which ensures high level of single-bit and multi-bit error detection and correction for memories operating in mission mode. This solution addresses the main requirements posed by automotive industry as well as successfully passed ISO 26262 certification with ASIL-D grade.

Given today's fast growing automotive semiconductor industry, this tutorial will discuss the implications of automotive test, reliability and functional safety requirements on all aspects of the SOC lifecycle: design, silicon bring-up, volume production, and particularly in-system functional safety. Today's automotive safety critical chips need multiple insystem self-test modes, such as power-on self-test and repair, periodic in-field self-test, advanced error correction, etc. This tutorial will cover these specific in-system modes and the benefits of selecting ISO 26262 certified solutions to ensure standardized functional safety requirements, while accelerating time to market for automotive SOCs.

Given the fast growing complexity and miniaturization of automotive SoCs, this paper presents functional safety challenges and related solutions for such SoCs. The paper is based on ISO 26262 standard and shows experimental results on a SoC example to demonstrate the advantages of the proposed solutions.

A functional safety solution based on multi-purpose built-in self-test and repair infrastructure for automotive SoCs is presented. This solution allows building a hierarchical network and managing it in multiple in-field test and repair modes.

Provides an abstract of the keynote presentation and may include a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings.

The semiconductor industry has been driving a major part of its growth through first the PC and more recently the mobile market. Unfortunately, the PC market is in decline and also the end of the growth curve for mobile products is in sight now that virtually everyone on the planet has a smartphone and/or tablet. Hence, the semiconductor industry is putting its bets on `Internet of Things' (IoT) as the next application wave that will allow them to sell a lot of silicon real estate. Although what exactly IoT encompasses is under definition and hence still volatile, the first emerging products depict an image which is quite different from the traditional microprocessors or smartphone SOCs: small but with ubiquitous presence, wirelessly connected, energy harvesting, equipped with smart sensors, secure, and low cost. All these aspects have a profound impact on the challenges, solutions, and associated trade-offs for testing IoT chips and provide rich grounds for research. This paper provides seven views from different angles.

Fault tolerant (or dependable) computing has always been an exciting research area in the intersection of computer science and engineering and electrical and electronics engineering. During the last two decades the applicability of the methods and tools that the fault tolerance research community produces has expanded to virtually all application domains. The type of fault tolerance methods employed in a computing system depend on: (a) the faults expected to affect the system, (b) the importance of errors in the system operation, (c) the design, cost and power budgets that can allocated to fault tolerance and reliable operation. New solutions and tools in fault tolerant computing are emerging to deal with the very broad spectrum of values that all (a), (b) and (c) can take in today's computing landscape.

From a structural viewpoint, an external memory linked to a system-on-chip (SoC) via high speed I/Os is typically composed of one or more memory dies/chips that interact with SoC using high bandwidth. Though testing an external memory and its high speed interconnects has always been a challenge, nevertheless this challenge became more critical with the increased use of high density packages, such as 2.5D or 3D. Not only fault detection but also fault diagnosis is important for fault type and fault location identification in external memories. In this paper an effective embedded test and diagnosis solution for external memory array and interconnects is proposed. The paper presents a new taxonomy for fault classification and new fault detection and diagnosis algorithm identifying external memory fault types and their locations. Finally it describes a built-in self- test (BIST) implementation which was successfully applied to DDR4 SDRAM.

The technology shrinking strategy below 20nm feature sizes adopted by the giants of the nowadays semiconductor industry has boosted the research on FinFET which is considered as an alternative to the conventional planar technology. This paper presents a comprehensive study carried out for FinFET-based memories using an advanced flow for fault modeling and test algorithm generation. Using this flow it has been shown that parameter variation (of process, voltage, temperature, frequency) has a significant impact on the fault coverage when dealing with FinFET-specific faults.

Due to their spatial structures, FinFETs have several advantages including controlled Fin body thickness, low threshold voltage variation, reduced variability and lower operating voltage. Because of the special structures of FinFET transistors, modern FinFET-based memories can lead to defects that require new test and repair solutions. Usually the existing approaches are not able to provide appropriate level of defect coverage and yield for FinFET memories. This presentation will discuss the design complexity, defect coverage and yield challenges of FinFET-based memories and introduce new methods to address them. This will include new design techniques, new FinFET specific defect and their coverage, as well as yield optimization infrastructure. Based on the obtained results, the presentation will also cover the synthesis of test algorithms for detection of diagnosis of FinFET memories s and built-in self-test infrastructure with a high efficiency of test and repair capability to ensure adequate yield improvement for FinFET-based memories. The presented methodology is validated by silicon data from multiple FinFET-based embedded memory technologies.

FinFET transistors are playing an important role in modern technology that is rapidly growing. Embedded memories based on FinFET transistors lead to new defects that can require new embedded test and repair solution. To investigate FinFET-specific faults the existing models and detection techniques are not enough due to a special structure of FinFET transistors. This paper presents a new strategy for investigation of FinFET-specific faults. In addition to fault modeling, a new method is proposed for test algorithm synthesis. The proposed methodology is validated on several real FinFET-based embedded memory technologies. Moreover, new faults are identified that are specific only to FinFETs.

In the year 2013, IEEE Test Technology Technical Council (TTTC) took an initiative to establish a forum involving young professionals (both from industry and academia) working in the broad domain of manufacturing test, diagnosis, debug, yield improvement and related areas. We organized panel meetings in conjunction with VLSI Test Symposium (VTS) and International Test Conference (ITC) last year to focus on the professional needs identified by the young colleagues that TTTC can help address. This is the third successive meeting of this forum that involves a diversified group of young professionals currently employed in the leading US semiconductor/EDA companies and in academia. The session will be held in town-hall format, organized by Dr. Alodeep Sanyal from Intel, and moderated by Dr. Yervant Zorian from Synopsys. The panelists will be involved in defining the charter for this newly-formed TTTC forum and establish a committee that will actively engage in monitoring these activities. Few of the focus areas include: (a) Create and maintain a webpage for Young Professionals (YP) Forum linked with the TTTC webpage, (b) Establish and nurture professional collaboration between young colleagues in academia and industry, (c) Create and maintain an employment opportunity database for graduating students. We invite everybody to attend the panel and voice their opinion from the audience.

One of the most important phenomena degrading Nano-scale Static Random Access Memory (SRAM) reliability is related to Negative-Bias Temperature Instability (NBTI). This paper presents the integration of the OCAS (On-Chip Aging Sensor) approach in the design methodology of 28nm single-port SRAM cores. The goal is to enhance the current test and repair on-chip infrastructure to detect SRAM aging during system lifetime. OCAS is able to detect the aging state of a cell in the SRAM array. The strategy is based on the connection of one OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM content after testing. SPICE simulations allowed us to analyze the OCAS sensitivity to detect early aging states in this very deep submicron technology, as well as the area, power and performance penalties due to the sensor insertion.

This paper introduces a new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms. It is proposed to describe all the periodicity and regularity rules in a form of a special Fault Periodicity Table (FPT) and March Test Template (MTT). FPT allows considering any large number of faults in one table and MTT allows obtaining March tests without using special tools for their generation.

IEEE Test Technology Technical Council (TTTC) takes an initiative to establish a forum involving young professionals working in the broad domain of test, diagnosis, yield improvement and related areas. We have formed a panel involving a diversified group of young professionals (recent PhD graduates from US and Canadian universities) currently employed in the leading US semiconductor and EDA companies. The session will be held in town-hall format, organized by Dr. Alodeep Sanyal from Synopsys and Dr. Yanjing Lin from Intel, and moderated by Dr. Yervant Zorian from Synopsys. The panelists will be involved in discussing the objectives of this newly-formed TTTC forum and the activities it should monitor. Some of the topics of discussion may include: (a) The benefits that TTTC can offer to the young professionals; (b) Establishing a connection between working professionals and graduate students that may provide research/mentoring opportunities for the professionals; (c) An actively maintained job requisition database exclusively available under TTTC for the student members to help them apply for a suitable job. The overall topic of discussion for this panel has been left quite open-ended for participants to propose their own ideas. We expect this panel will identify the future direction and activities for the TTTC Young Professionals Forum.

As process technologies continue to shrink and design complexity grows, today's designs present a unique set of test challenges including higher test costs, higher power consumption during test, lower design productivity and new defects at small geometries. The designs are larger and using multiple processor cores in SoCs to enable the next generation of mobile internet devices. Each core contains its own compression logic to lower test costs by reducing test application time and test data volume. But these cores all compete for chip-level test resources, limiting pin access at the core level. Techniques are therefore needed to implement architectures that make efficient use of limited test resources while maximizing test coverage and minimizing pattern count.In addition, today's demanding video centric applications require more memory, resulting in a shift from the logic-dominant chips of the past to memory-dominant chips. Embedded memories are the densest components within a SoC, accounting for more than 50 percent of the chip area. Implemented using aggressive design rules, embedded memories tend to be more susceptible to manufacturing defects and field reliability problems than any other core on a chip. Therefore, the overall yield of an SoC depends heavily on the memory yield, and securing high memory yield is critical to achieving lower silicon cost. Embedded memory test requires solutions capable of addressing yield and reliability needs such as fault detection, repair at the manufacturing level, diagnosis for process improvement and field repair capabilities-all with minimal impact on the functional design.

This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14 nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor nodes, routers and links of single-chip massively parallel tera-device processors could comprise timing faults (such as delay faults or clock skews); a large percentage of these parts are affected by catastrophic failures; all parts experience significant performance degradations over time; and new catastrophic failures occur at low MTBF.

In this paper, all linked and unlinked static and two-operation dynamic faults are considered. A classification for their description is introduced. To generate a test algorithm for detection of all the considered faults, it was shown that it is not an easy problem. For this purpose, a new structure-oriented method is developed. Based on the proposed method, an efficient test algorithm March LSD of complexity 75N is generated for the detection of the considered linked static and dynamic faults.

This paper presents a robust solution for test and repair of embedded memories. The STAR (Self-Test and Repair) Memory System solution is developed within Synopsys Design Ware allowing users to create, integrate and verify embedded memory test and repair IP in system on chips. The key components and features of the SMS are discussed.

Minimal March test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an extension of an existing BIST architecture for testing of static random access memories (SRAMs) and read-only memories (ROMs). This generic BIST architecture additionally supports the following important CAM specific features: power buffer-zones, multicycle compare operations, half/quarter words and walking patterns.

The external specifications of an IC (functions, clock rate, power consumption, etc.) determine the competitiveness of a product. To be successful and profitable in the IC business, designers need to "out-design" their competitors. Usually, Design-For-Manufacturing (DFM) is discussed as a yield improvement strategy, but what is the value of DFM from a competitive point of view? Can DFM gives designers a competitive lever by helping them decide how far to push a design without creating a manufacturing disaster? Can DFM be used to optimize designs rather than just identify hot spots?

Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D stacked ICs (3D-SICs) based on through-silicon vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.

Previously, a minimal algorithm of length 70 N, N is the number of memory bits, was proposed for a subclass of dynamic faults. In this paper, a March-based fault location and full diagnosis algorithm of complexity 88 N+29 is proposed for the same subclass of dynamic faults in bit-oriented SRAMs.

Core-based design and reuse are the two key elements for an efficient system-on-chip (SoC) development. Unfortunately, they also introduce new challenges in SoC testing, such as core test reuse and the need of a common test infrastructure working with cores originating from different vendors. The IEEE 1500 Standard for Embedded Core Testing addresses these issues by proposing a flexible hardware test wrapper architecture for embedded cores, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Several intellectual property providers have already announced IEEE Standard 1500 compliance in both existing and future design blocks. In this paper, we address the problem of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE Standard 1500. This step is mandatory to fully trust the wrapper functionalities in applying the test sequences to the core. We present a systematic methodology to build a verification framework for IEEE Standard 1500 compliant cores, allowing core providers and/or integrators to verify the compliance of their products (sold or purchased) to the standard.

The Test industry has come a long way over the past few decades. As a whole we have made great strides in the areas of:

Design and manufacturing flows and methodologies are directly impacted by the demand for emerging SoCs with increasing performance and parallelism. Moving to new semiconductor technology nodes can significantly affect the choices of suppliers. This session will provide an overview of changing needs and corresponding management decision criteria to make the right choices from a pool of alternate options for flows, methodologies and suppliers.

Consumer electronics chips are the technology drivers today. They require different types of optimizations and thus the need to adopt emerging solutions to meet such requirements. Optimizing for high volume production, low power, and shrinking sizes necessitate adequate trade-off analysis and technical/business decision making by management. The lead managers in this session will discuss today's emerging solutions and their economic impact.

The class of dynamic faults has been recently shown to be an important class of faults for the new technologies of random access memories (RAM) with significant impact on DPM levels. Very little research has been done in the design of memory test algorithms targeting dynamic faults. Two March test algorithms of complexity 11N and 22N, N is the number of memory cells, for subclasses of two-operation single-cell and two-cell dynamic faults respectively were proposed earlier by other authors. Also a March test of complexity 100N was proposed by them for detection of two-cell dynamic faults with two fault-sensitizing operations both applied on the victim or aggressor cells. In this paper, for the first time, minimal March test algorithms are proposed for two-operation single-cell and two-cell dynamic faults. The previously known March test algorithm for detection of two-operation two-cell dynamic faults is improved by 30N

In this paper, a new notion of 2-composite static faults covering all unlinked and (realistic) linked static faults is introduced. We have introduced 120 new linked fault primitives missing in the paper by Hamdioui et al (IEEE TCAD 2004), thus extending the universe of linked fault primitives known before by 25%. A march test algorithm of length 23N (N - number of memory words) for detection of linked static faults in random access memories is proposed. It reduces the length of a previously known algorithm (Hamdioui et al., IEEE TCAD 2004) by 18N. We proved the proposed test is of minimum length

Today’s system-in-package (SiP) technology involves the system integration of multiple die from various technologies into a common package. This session will present SiP applications and their design and test practices from the major SiP companies. The presentations include issues for SiP, and trade-offs between SiP vs. POP vs. SOC integration for cell phone applications.

While test technology is directly linked into semiconductor manufacturing, the incorporation of test solutions into the design needs to take place during different stages of chip design flow. These distributed DFT efforts start from IP design stages and end up at the final tape-out stage. As the electronic design automation flow expands from both ends front and back, and as the testability requirements for third party IP acquisition matures, where should the future of DFT industry be? Would it be in point tools plugged into different stages of the design flow? or would it be an integral part of the IP delivery? or would it be merged into adjacent design automation solutions? How would this impact on the future of DFT, as an industry sector? This panel will look at the changing requirements in this test technology sector and its business implications.

In addition to designing the functionality, today’s SOC necessitates designing for manufacturability, yield and reliability. Such requirements are fundamentally transforming the current SoC design methodology techniques for enhancing manufacturability, yield and reliability or "DFX" to include yield enhancement techniques, resolution enhancement techniques, new or restricted design rules, variability-aware design, and the addition of a special family of embedded IP blocks, called infrastructure IP blocks. The latter blocks are meant to ensure manufacturability of the SoC and to achieve adequate levels of yield and reliability. The infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This tutorial analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of the above DFX techniques. Then, it concentrates on several examples of each of these techniques.

Different applications for today's chips require different type of optimizations and thus the need to adopt emerging products and solutions to meet such requirements. Optimizing for low power, for high yield, for reduced soft error or minimal bring up time necessitate adequate trade-off analysis and technical/business decision making by management. The lead managers in this session will discuss today's emerging solutions and their economic impact.

Moving to new semiconductor technology nodes can dramatically impact the business performance of the SoC company, and its age-old design and manufacturing flows and methodologies. It can also significantly affect its choices of suppliers. This session will provide an overview of changing needs and corresponding management decision criteria to make the right choices from a pool of alternate options.

Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to update their knowledge on memories. This hot topic paper provides an embedded tutorial on embedded memories, in terms of what is new and coming versus what is old and vanishing, and what are the associated design, test, and repair challenges related to using embedded memories.

Several years ago, the vertically integrated semiconductor companies started to disaggregate into separate sectors, such as fabless, EDA, IP, Design Services, DFT, foundry, and test & packaging houses. On the one hand the disaggregated sectors are in the process of merging and optimizing their product lines, roles and responsibilities On the other hand, certain companies are trying to reverse the trend by reaggregating some of the disaggregated sectors. Will the reaggregation trend dominate? Which trend enables a better semiconductor market growth? Which trend allows superior technological offerrings? Who will be the shark?

On-line testing approaches can today be useful when designing circuits with severe security constraints. The reasons are summarized in the introduction to the special session on secure implementations (in these proceedings). The presentations in this special session aimed at introducing the specific concerns related to security as well as some approaches used to protect the circuits and to validate their robustness for certification. This panel aims at discussing in more details how on-line testing techniques can help in improving security and how the achieved level of security can be evaluated at different stages in the design flow. Various aspects are covered by the participants, including: counter-measures for fault attacks in hardware cryptographic primitives, design for test versus design for security, use of fault injection tools in evaluating the robustness against attacks and validation of security at the system level.

Soft errors are a major challenge to robust design. Conventionally, designs with high level requirements for reliability and availability required protection against soft errors. However, the scaling level reached with today's nanometer technologies is moving the soft error protection requirements to SoC designs for a wide range of applications. This paper discusses the soft error challenge, its implication on SoC design practices and possible approaches to create a robust SoC design.

A set of SoC test challenges have been introduced a decade ago, as embedded core based design and hence multi-core SoCs started to become popular. The topic of this panel is to analyze the SoC test challenges and determine if they have already been solved or not

Integrating numerous IP cores into a SoC design is a complex activity from the design-for-testability point of view. Also, accessing and exercising test and diagnosis patterns on each IP core during the manufacturing phases is a major challenge. Designing the IEEE 1500 standard into the IP core and leveraging it during the DFT integration and manufacturing phases drastically simplify these challenges. This paper demonstrates the use of IEEE 1500 in embedded memory IP cores, and describes how it can be leveraged in a SoC during its design and manufacturing phases

New minimal March test algorithms are proposed for detection of (all) unlinked static faults in random access memories. In particular, a new minimal March MSS test of complexity I8N is introduced detecting all realistic simple static faults, as March SS (22N), (S. Hamdioui, van de Goor, Rodgers, MTDT 2002).

Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typically time-consuming due to the required pause time that needs to be introduced in the test session. This paper proposes a novel technique, referred to as pre-discharge write test mode (PDWTM), that effectively integrates the testing of DRF within "regular" March algorithms such that the rate (speed) of the latter remains unaltered. That is, the PDWTM enables DRF testing without incurring the additional cycles or pauses in the March test execution thereby enabling additional coverage at no expense in terms of overall test time. We show that DRFs can be easily detected by pre-discharging bit lines before a write operation. Here, the PDWTM is evaluated using both high-speed and low power memory cells, representing two extreme cases based on the typical memory design methodologies.

Today's SoC designs use significant outsourced IP and manufacturing and the overall SoC yield can be bounded by the yield of the embedded memories often provided by third party sources. Who is responsible for ensuring better memory yield - the memory IP provider, the foundry, the design team, the test house, the library provider? How can yield be maximized? What are the shortcomings of the current methods and what new investments, strategies, and collaboration are required at the design stage, on the manufacturing floor, and in the field ? How do these investments relate to yield improvement ?.

A methodology for design and evaluation of redundancy allocation algorithms based on prime algorithms is proposed for memory devices with spare elements. The methodology can be applied to any memory device with spare elements. It allows the design of simple but effective built-in redundancy allocation (BIRA) algorithms working "on-the-fly" with BIST. The methodology allows also reasonable trade-off between repair coverage and hardware/time complexity during the implementation. A basic toolset for design and evaluation of BIRA algorithms based on the proposed methodology is developed and preliminary results of experiments on the application of the tool for self-test and repair (STAR) type SRAM memories are adduced.

Increasingly dense SRAMs of various bit capacities, embedded within current and future systems-on-a-chip (SoC) designs, command not only additional complexity due to required redundancy schemes, but also present serious challenges in regards to testing. In particular, the time needed for testing data retention faults (DRFs) and non-DRFs is growing rapidly. In this paper, we consider the overall production gain (OPG) and delay time associated with the testing of DRFs as the two selection factors for classifying embedded SRAMs, where OPG quantifies the trade-offs between yield and redundancy area overhead. These embedded SRAMs are categorized into four categories for testing non-DRFs and DRFs. Since both factors above are related to memory capacity, the four categories are named as very small, small, large, and very large types. According to this simple classification, we generate a set of four March test algorithms from an existing March SRD algorithm for each category respectively. As a comparison with March SRD, our investigations reveal that test time can generally be at least halved down to 22 nm technology for all capacity e-SRAMs with different IO numbers without losing defect coverage. The evaluation results also show that this reduction ratio is always no less than 50% for those with larger and larger and larger capacity predicted for future e-SRAMs in ITRS documents no matter what complex the comparison algorithms besides March SRD are.

We consider circuits represented as interconnections of logic blocks. In such circuits, the goal of fault isolation is to identify which one of the blocks is faulty based on a faulty output response produced by the circuit. We study this issue and demonstrate that perfect or close-to-perfect fault isolation is possible with tests that propagate fault effects through pairs of blocks. We relate this phenomenon to the numbers of fault effects observed on the circuit outputs for faults in different blocks. For cases where fault isolation is not perfect, we insert observation points to ensure perfect fault isolation. We also study the number of tests required to achieve perfect fault isolation. The study is performed for single stuck-at faults in combinational (or full scan) blocks.

Summary form only given. In addition to the functional IP cores, today's SoC necessitates embedding a special family of IP blocks, called infrastructure IP blocks. These are meant to ensure the manufacturability of the SoC and to achieve adequate levels of yield and reliability. The infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This keynote address analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of such infrastructure IP. Then, it concentrates on certain examples of such embedded IPs for detection, analysis and correction.

Embedded processor testing techniques based on the execution of self-test routines, have been recently proposed as an effective alternative to classical hardware Built-In Self Test. Software-based self-testing provides atspeed testing capability and does not add hardware or performance penalties. It efficiently partitions the testing task between external testers and internal processor resources. In this paper we analyze the application of a softwarebased self-testing methodology to different implementations of a complex embedded processor architecture. We demonstrate that such a methodology provides high test quality in different processor implementations with low test development and low test application costs. 1

We consider the problem of built-in test pattern generation for non-isolated scanned cores. When two such cores are interconnected, a block of combinational logic that spans both cores may be created. Our goal is to provide a solution for built-in testing of logic that spans multiple cores. Starting from a given test-pattern generator (TPG), we propose a design-for-testability approach to improve the fault coverage achieved by the TPG. This approach is based on designing the interfaces between pairs of cores such that they support the testing of both cores. The proposed approach does not require any modifications to the cores themselves. In a vast majority of the benchmark circuits considered, the proposed approach results in 100% fault coverage.

In addition to the functional IP cores, today's SOC necessitates embedding a special family of IP blocks, called Infrastructure IP blocks. These are meant to ensure the manufacturability of the SOC and to achieve adequate levels of yield and reliability. The Infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This paper analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of such Infrastructure IP. It also describes several examples of such embedded IPs for detection, analysis and correction.

Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning technique for sharing the testing task of complex systems-on-chip (SoC) between slow, inexpensive testers and embedded code stored in memory cores of the SoC. We introduce an efficient methodology for processor cores self-testing which requires knowledge of their instruction set and Register Transfer (RI) level description. Compared with functional testing methodologies proposed in the past, our methodology is more efficient in terms of fault coverage, test code size and test application time. Compared with recent software based structural testing methodologies for processor cores, our methodology is superior in terms of test development effort and has significantly smaller code size and memory requirements, while virtually the same fault coverage is achieved with an order of magnitude smaller test application time.

Summary form only given. Design methodologies for large designs produce circuits that consist of interconnections of functional blocks. If the blocks are large, as in core-based designs, they may be isolated for testing purposes (e.g., by test wrappers) such that different blocks can be tested independently. However, even if a test wrapper exists, it is advantageous to test functional paths that go through two or more blocks by using test vectors that propagate fault effects through several blocks. This contributes to testing of defects that cannot be detected if each block is tested separately. One of the issues that arises when several blocks are tested by the same test is that of fault isolation. If a test that propagates fault effects through blocks C/sub 1/ and C/sub 2/ produces a faulty response on the outputs of C/sub 2/, the goal of fault isolation is to identify which one of C/sub 1/ and C/sub 2/ is faulty. Fault isolation is perfect if every faulty response on the outputs of the circuit can be uniquely attributed to a single block. This happens when every pair of faults belonging to different blocks is distinguishable. If faults of different blocks remain undistinguished, fault isolation is not possible when responses equal to the responses produced by these faults are produced by the circuit-under-test. It may appear that tests for several non-isolated blocks will not be able to isolate faults. In this work, we study this issue and demonstrate that perfect or close-to-perfect fault isolation is possible with tests that propagate fault effects through several blocks.

Today's system-on-chip typically embeds memory IP cores with very large aggregate bit count per SoC. This trend requires using dedicated resources to increase memory yield, while containing test and repair cost and minimizing time-to-volume. This paper summarizes the evolution of such yield optimization resources, compares their trade-offs, and concentrates on on-chip infrastructure IP. To maximize the repair efficiency, this infrastructure IP needs to leverage the memory design knowledge and the process failure data. The ideal solution is to integrate the memory IP and its infrastructure IP into a single composite IP that yields itself effectively.

Instruction-based self-testing of embedded processor cores provides an excellent technique for balancing the testing effort for complex Systems-on-Chip (SoC) between slow, inexpensive external testers and embedded code stored in memory cores. In this paper we apply our efficient methodology for processor core self-testing based on the knowledge of its instruction set architecture and register transfer level description on a common accumulator-based processor core benchmark We also demonstrate that our methodology is superior in terms of test development effort and has significantly smaller code size and memory requirements, while the same fault coverage is achieved with an order of magnitude smaller test application time compared with a recently published structural methodology for processor core self-testing.

A deterministic software-based self-testing methodology for processor cores is introduced that efficiently tests the processor datapath modules without any modification of the processor structure. It provides a guaranteed high fault coverage without repetitive fault simulation experiments which is necessary in pseudorandom software-based processor self-testing approaches. Test generation and output analysis are performed by utilizing the processor functional modules like accumulators (arithmetic part of ALU) and shifters (if they exist) through processor instructions. No extra hardware is required and there is no performance degradation.

Proposes a new and original FPGA architecture with testability facilities. It is first demonstrated that classical FPGA architectures do not allow one to efficiently implement sequential circuits with a scan chain. It is consequently proposed to modify the architecture of classical FPGAs in order to create an implicit-scan chain into the FPGA itself called implicit scan FPGA (IS-FPGA). Using this new FPGA architecture, any sequential circuit implemented into the FPGA is 'implicitly scanned'. An original and optimal implementation of the proposed architecture is given with minimum area overhead and absolutely no delay impact. Additionally the technique is transparent for the user as well as for the FPGA mapping tools. Finally, it is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits.

The modified Booth array multiplier is the most ubiquitous multiplier architecture in the datapaths of either general purpose microprocessors or specialized Digital Signal Processors. Sequential fault testing for Booth array multipliers has never been proposed in the past. In this paper, we present two BIST architectures for modified Booth array multipliers with respect to the Realistic Sequential Cell Fault model (RS-CFM). The first BIST architecture aims to resolve the test invalidation problem to the largest possible extent, while the second one aims to test cost reduction. Both BIST architectures achieve very high sequential fault coverage and impose moderate hardware and delay overhead. Simplified variations of the two BIST architectures are also presented for the non-recoded signed array multipliers. Thus, the proposed BIST architectures offer a universal BIST solution that covers the totality of signed array multipliers: non-recoded and recoded.

A boundary scan-based algorithm is presented for testing iterative arrays of identical units such as integrated circuits on silicon wafers, MCMs fabricated on a large area panel, and multiprocessor systems. As all the units are similar, it is critical that the test process be parallelized in order that multiple units may be tested for the cost of testing one unit. With this objective in mind, we propose a parallel and pipelined boundary scan standard-based scheme for testing all units simultaneously. In this scheme, the test vectors and the corresponding correct-response vectors are both scanned into the scan chain of the units in an interleaved fashion, optimally utilizing the resources of every chain to test all units. The comparison of the expected versus the observed response of a unit is performed locally at each unit. Our algorithm provides an order of magnitude speed-up in test time over conventional boundary scan based testing schemes. Further, as the number of chains increases, the test time tends asymptotically toward the optimal. The complete design of the test architecture is also presented.

A novel scheme of synthesizing nonlinear feedback shift register structures that can be superimposed on the boundary of the component of a system under test to generate interconnect switching activities that resemble real life interconnect switching profiles is proposed. The goal is to perform at-speed interconnect test while simultaneously capturing the dynamic switching effects such as crosstalk and ground bounce, as accurately as possible during interconnect built-in self-test. A library of nonlinear feedback shift register structures called precharacterized test pattern generators (P-TPGs) is constructed. Components of P-TPGs can be modeled using Markov chain and can be interconnected together in specific ways to recreate the switching activity profile of the interconnections being tested. The unique advantage of this scheme is that there is no simulation overhead since P-TPG components are precharacterized by solving Markov equations analytically. An integrated genetic algorithm-based search and optimization technique for finding the best P-TPG component among various possible implementations and matching its activity profiles with those of the interconnections under test has been designed and implemented synthesis for testability allows generation of the worst case interconnect switching activities. Experimental results confirm the validity of our approach.

The objective of this paper is to generate an Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault." Then, it is commented that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is also commented that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.

A major challenge in realizing core-based system chips is the adoption and design-in of adequate test and diagnosis strategies. This tutorial paper discusses the specific challenges that come with testing deeply embedded reusable cores supplied by diverse providers, who often use different hardware description levels and mixed technologies. The paper describes a general test access architecture for embedded cores, and covers the current standardization efforts in this domain. In addition, we give an overview of the emerging EDA developments in SOC test, and illustrate the current industrial practices by means of two case studies.

Power in processing cores (microprocessors, DSPs) is primarily consumed in the datapath part. Among the datapath functional modules, multipliers consume the largest amount of power due to their size and complexity. We propose a low power BIST scheme for datapaths built around multiplier-accumulator pairs. The target is low average power dissipation between successive test vectors. This is achieved by taking advantage of the regularity of multiplier modules and achieving very high fault coverage by a linear-sized test set with as small as possible input switching activity. The proposed BIST scheme is more efficient than pseudorandom BIST for the same high fault coverage target. Up to 77.2% power saving is achieved in the set of experimental results provided in the paper.

In this paper, we give an overview of the trade-off to improve yield and optimize silicon manufacturing cost. The specific technology focus is on large embedded memories in complex ASIC or system-on-chip designs. Embedded capabilities for test, redundancy analysis and repair are shown as design-for-manufacturability features needed for large embedded memories in VDSM design.

Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a single chip. Being able to rapidly develop, manufacture, test, debug and verify complex SOCs is crucial for the continued success of the electronics industry. This growth is expected to continue full force at least for the next decade, while making possible the production of multimillion transistor chips. However, to make its production practical and cost effective the industry road maps identify a number of major hurdles to be overcome. The key hurdle is related to test and diagnosis. This embedded tutorial analyzes these hurdles, relates them to the advancements in semiconductor technology and presents potential solutions to address them. These solutions are meant to ensure that test and diagnosis contribute to the overall growth of the SOC industry and do not slow it down. This embedded tutorial in addition presents the state of the art in system-level integration and addresses the strategies and current industrial practices in the test of system-on-chip. It discusses the requirements for test reuse in hierarchical design, such as embedded test strategies for individual cores, test access mechanisms, optimizing test resource partitioning, and embedded test management and integration at the System-on-Chip level. Processor cores being one of the most common cores embedded in a SOC, issues related to self-testing embedded processor cores are addressed. Future research challenges and opportunities are discussed in enabling testing of future SOCs which use deep submicron technologies.

Proposes HD/sup 2/BIST, a complete hierarchical framework for BIST scheduling, data patterns delivering, and diagnosis of a complex system including embedded cores with different test requirements as full scan cores, partial scan cores, or BIST-ready cores. The main goal of HD/sup 2/BIST is to maximize and simplify the reuse of the built-in test architectures, giving the chip designer the highest flexibility in planning the overall SoC test strategy. HD/sup 2/BIST defines a test access method able to provide a direct "virtual" access to each core of the system, and can be conceptually considered as a powerful complement to the P1500 standard, whose main target is to make the test interface of each core independent from the vendor.

In this paper, we describe an experiment about structural testing of two XILINX FPGAs families. In our practical approach, the FPGA is divided into different arrays: an array of logic cells, an array of interconnect cells and an array of RAM cells. For each part, we use a specific fault model and we generate test configurations and test vectors for the considered models. In each case, for each array, we try to minimize as much as possible the number of test configurations because re-programming FPGAs is really time consuming.

System chips are increasingly designed by embedding reusable cores. A core-based test strategy for such ICs is often attractive and sometimes even mandatory. IEEE P1500 SECT is a standard under development that standardizes a core test language and a core wrapper, in order to facilitate plug-n-play core testing. In this paper, we describe how one standard supports both easy integration and interoperability as well as flexibility and scalability. Possible usage scenarios of the standard for core providers, core users, and EDA tool developers are sketched.

A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (TAM), the core test wrapper forms the test access infrastructure to embedded reusable cores. Various company-internal as well as industry-wide standardized but scalable wrappers have been proposed. This paper deals with the design of such core test wrappers. It gives a general architecture for wrappers, and describes how a wrapper can be built up from a library of wrapper cells which are selected on basis of the terminal types of the core. We show that the ordering and partitioning of wrapper cells and core-internal scan chains over TAM chains determine the test time of the core. An heuristic approach for the NP-hard problem of partitioning the TAM chain items for minimal test time is presented and its usage is illustrated by means of an example. Finally we sketch how wrapper generation and verification can be automated.

Power in processing cores (microprocessors, DSPs) is primarily consumed in the functional modules of the datapath. Among these modules, multipliers consume the largest amount of power due to their size and complexity. We propose low power BIST schemes for datapath architectures built around multiplier-accumulator pairs, based on deterministic test patterns. Two alternatives are proposed depending on whether the target is low energy dissipation during a BIST session or low power dissipation (i.e. average energy dissipation between successive test vectors). The proposed BIST schemes are more efficient than pseudorandom BIST for the same high fault coverage target. Up to 78.33% energy saving is achieved by the proposed low energy BIST scheme and up to 82.22% power saving is achieved by the proposed low power BIST scheme, compared with pseudorandom BIST.

Iterative Logic Arrays (ILAs) are widely used in the datapath parts of digital circuits, like general purpose microprocessors, embedded processors, and digital signal processors. Testing strategies based on more comprehensive fault models than the traditional combinational fault models have become an imperative need in CMOS technology. In this paper, first, we introduce a comprehensive, cell-level, sequential fault model suitable for ILAs, termed Realistic Sequential Cell Fault Model (RS-CFM). RS-CFM drastically reduces test complexity compared to exhaustive two-pattern testing proposed so far in the literature for sequential ILA testing, without sacrificing test quality. In addition, it favors robustness of sequential test sets both at the cell and the array levels. Second, a new Automatic Test Pattern Generator (ILA-ATPG) based on RS-CFM for the case of one-dimensional ILAs is presented. ILA-ATPG can handle all classes of one-dimensional ILAs: unilateral or bilateral ILAs, with or without vertical inputs/outputs. Based on a graph model, ILA-ATPG explores the C-testability and linear-testability of the ILA under test and resolves the test invalidation problem constructing robust test sequences. The efficiency of ILA-ATPG is demonstrated through a comprehensive set of experimental results over all classes of one-dimensional ILAs, including all practical one-dimensional ILAs, as well as a number of more complex benchmarks.

This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA. The proposed approach is applied to the XILINX SPARTAN, 4000 and 3000 families. On these examples of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then for a single logic cell, and finally for the m/spl times/m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configurations for a single logic cell. An approach is then described to define a minimum number of test configurations for a logic cell knowing the test configurations of its logic modules. This approach gives only 4 test configurations for the XILINX Spartan, 5 for the 4000 and 4 for the 3000 while the previous published works concerning Boolean testing of these FPGA families give 8 for the 4000 and 5 for the 3000.

Summary form only given. Progress in technological scaling allows the integration into a single chip of hundreds of millions of transistors, moving quickly to the multi-billion transistor capacities. Achieving acceptable quality and reliability levels for these complex products is one of the most critical issues that need to be faced. Testability is therefore a key factor that could limit these trends if not addressed adequately. At these levels of complexity external testing is becoming infeasible due to ATPG limitations. At the same time, the scan approach is losing interest due to the increasing length of scan chains (and thus test length), and low test application speed. At-speed test is a major limitation at a context where increasing clock frequencies (moving quickly to the multi-GHz domain), are making timing faults predominant. Automatic Test Equipment (ATE) is another important limitation, since, although its very high cost, it does not offer the memory capacities/depth and test application speed required for testing present day ICs. Under these constraints, the only realistic issue is to extend the BIST practice beyond memory testing. This requires new developments on logic BIST for increasing fault coverage while containing hardware cost. Furthermore, new developments on fault modeling, fault simulation, and ATPG tools are needed to encounter for timing faults, cross talk, ground bounce and other spurious faults. These developments should be oriented towards a BIST approach.

Wallace free summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex systems on chip. Testing of such multiplier cores deeply embedded in complex ICs requires the utilization of a BIST architecture that can be easily synthesized along with the multiplier by the module generator. In this paper we introduce an effective BIST architecture for fast multipliers that completely complies with this requirement. The algorithmic BIST patterns that this architecture generates guarantee a fault coverage higher than 99%. The required test pattern generator consists of a simple fixed-size binary counter, independent of the multiplier size. Accumulator-based compaction is adopted since multipliers and adders co-exist in most datapath architectures.

The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. In usual SRAM-based FPGAs, Configurable Interface Modules (CIMs) can be found between the global interconnect and inputs of the logic cells (input CIMs) or between output of the logic cells and the global interconnect (output CIMs). It is demonstrated that an input CIM that connects N/sup in/ segments to a logic cell input requires N/sup in/ test configurations and that an output CIM that connects a logic cell output to N/sup out/ segments requires 2 test configurations. Then, it is proven that a set of K/sup in/ input CIMs can be tested in parallel making the number of required test configurations equal to N/sup in/. In the same way, a set of K/sup out/ output CIMs is shown to require only 2 test configurations if N/sup out/>K/sup out/. Finally, it is shown that the complete mXm array of logic cells with K/sup in/ input CIMs and K/sup out/ output CIMs can be tested with only N/sup in/ test configurations using the XOR tree and shift register structures.

This paper proposes HD-BIST, a complete framework to support the definition of the scheduling strategy and mechanism of the BISTed blocks of a complex system. Three different layers are presented, to define the HD-BIST approach in terms of a set of high-level BIST scheduling primitives, a communication protocol, and a possible hardware implementation, respectively.

Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language. This paper provides a preliminary, unapproved view on IEEE P1500. The standard is still under development, and this paper only reflects the view of five active participants of the Standardization Committee on its current status.

We consider issues related to the testing of a legacy core embedded in user-defined logic. We assume that the only information available about the core is its test set. We provide procedures for testing the core and its surrounding logic without adding DFT logic. The procedures maximize the information extracted from the test set given for the core, in order to maximize the fault coverage achieved without DFT. We also describe DFT insertion procedures. The core and the surrounding logic are considered simultaneously during DFT insertion to minimize the amount of DFT logic required.

Sequential fault testing approaches for array multipliers proposed in the past target only external testing and impose significant hardware overhead due to excessive DFT modifications. In this paper we present, for the first time, a BIST architecture which does not require any DFT modifications in the multiplier structure and provides a fault coverage larger than 99% for a comprehensive sequential fault model (RS-CFM) for any multiplier size. Both robust and non-robust testing are considered. The applicability of the BIST architecture is further justified considering the case of the transistor stuck-open fault model, where a fault coverage larger than 99% is also achieved in any case.

An effective built-in self-test (BIST) scheme for parallel multipliers (array and tree) is proposed. The new scheme combines the advantages of deterministic and pseudorandom testing and avoids their drawbacks. No modifications to the multiplier structure are required. A guaranteed very high fault coverage of a comprehensive cellular fault model is achieved. The results do not depend either on the gate-level implementation of the multiplier cells or the architecture of the multiplier (whether it is a carry-propagate or carry-save array multiplier or a tree multiplier) or on the multiplier size. A small deterministic test set of highly regular test vectors is used which exploits the inherent regularity of the multiplier architecture. The regularity of the test vectors allows for their on-chip generation with a very small hardware overhead, which is equivalent to the hardware overhead of pseudorandom testing.

This paper address the problem of testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. The Configurable Interface Modules (CIMs) are assumed to be implemented with FPGA multiplexers but the results can be easily extended to any type of interface module. First, it is demonstrated that an address bit Configurable Interface Multiplexer requires N=2/sup n/ test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable Interface Modules with n address bits is analysed and it is proven that the set of CIMs can be tested in parallel making the number of required test configurations equal to N=2/sup n/. Third, it is shown that the complete circuit, i.e. a m/spl times/m array of sets of k Configurable Interface Multiplexers with n address bits can be tested with only N=2/sup n/ test configurations using the XOR tree and shift register structures.

A major challenge in realizing core-based system-chips is theadoption of adequate test and diagnosis strategies. This paperfocuses on the current industrial practices in test strategiesfor system-chips. It discusses the challenges in testingembedded cores, the testing requirements for individualcores, and their test access mechanisms. It also covers theintegrated test strategies for system-chips based on reusablecores. In addition to the state-of-the-art practices intestability schemes, this paper covers the currentstandardization efforts for embedded core test interfacemechanisms.

In this paper, a new compaction technique based on signature analysis is presented. Rather than comparing the final signature with the expected one after the test is completed, the binary output of the MISA is converted into an alternating binary signal by two simple cover circuits. An error is indicated whenever the alternation of the output signal is disturbed. This technique results in a higher fault coverage, improved fault diagnosis capability, a greater test autonomy in core-based designs, and early fault notification.

This paper presents a novel technique for testing Field Programmable Gate Arrays (FPGAs), suitable for use in the case of frequent FPGA reuse and rapid dynamic modifiability of the implemented function.

This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic test configurations to fully test the whole matrix of CLBs. In the proposed test configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of test configurations 8 is fixed and independent of the FPGA size.

No abstract available.

The issue of performance testing of MCM interconnections is becoming very important due to the fact that hitherto second order effects such as ground bounce, crosstalk and switching noise are playing dominant roles in current design methods due to shrinking dimensions, lower supply voltages, higher clock speeds and higher density packaging. We propose a novel scheme for synthesizing nonlinear feedback shift register structures that can be superimposed on the boundary scan cells of ICs to generate MCM interconnect switching activities that resemble real life interconnect switching profiles. The goal is to perform at speed MCM interconnect test while simultaneously capturing the dynamic switching effects referred to earlier as accurately as possible during interconnect BIST. A library of nonlinear feedback shift register structures called Precharacterized Test Pattern Generators (P-TPG) is constructed. Components of P-TPGs are interconnected together in specific ways to recreate the switching activity profile of the interconnections being tested. An optimization algorithm for matching the P-TPG component activity profiles with those of the interconnections under test has been designed, and implemented experimental results confirm the validity of our approach.

As the density of embedded memory increases, manufacturing yields of integrated circuits can reach unacceptable limits. Normal memory testing operations require BIST to effectively deal with problems such as limited access and "at speed" testing. In this paper we describe a novel methodology that extends the BIST concept to diagnosis and repair utilizing redundant components. We describe an application using redundant columns and accompanying algorithms. It allows for the autonomous repair of defective circuitry without external stimulus (e.g. laser repair). The method has been implemented with negligible timing penalties and reasonable area overhead.

A general description of an enhanced scheme for designing completely self-testable MCMs is given. It allows performance testing and diagnosis of MCM interconnections for dynamic effects. This scheme is based on embedding of cascadable test pattern generators and reconfigurable signature analyzers into the design of MCM dies. A theory of partitioning of linear registers is applied to devise a two phase distributed diagnosis strategy The design of a novel MISR reconfiguration scheme that enables high diagnosis resolution, is presented. Simulation results obtained confirm the effectiveness of our BIST technique.

This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2/sup N/ memory cells is proposed taking into account the LUT and RAM modes. Concerning the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the march tests. We also propose a unique test configuration called 'pseudo shift register' for mxm arrays of modules. In this configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called 'shifted MATS++' is described. Concerning the LUT mode, we use the concept of non-redundant test that proposes to test in LUT mode the parts of the module not tested in RAM mode. Under this hypothesis, it is demonstrated that the test of a single module as well as the test of an mxm array of modules require only 3 test configurations. Using our solution, the test of a complete array of mxm LUT/RAM modules requires 4 test configurations independently of the size of the array and of the modules.

Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced by a design style based on embedding large reusable modules, the so-called cores. This core-based design poses a series of new challenges, especially in the domains of manufacturing test and design validation and debug. This paper provides an overview of current industrial practices as well as academic research in these areas. We also discuss industry-wide efforts by VSIA and IEEE P1500 and describe the challenges for future research.

Traditional combinational fault models are not sufficient to detect to most common failure mechanisms in CMOS Iterative Logic Arrays (ILAs). The Realistic Sequential Cell Fault Model (RS-CFM) provides a comprehensive, robust test methodology for ILAs. It also satisfies the requirements for low test complexity and cell implementation independence. Adopting RS-CFM, we first provide sufficient conditions for two-dimensional (2D) ILAs to be robustly testable for first time in the literature. Then, we propose sufficient modifications to the carry-save and carry-propagate array multipliers so that they can be treated robustly with respect to RS-CPM with a test set of linear size.

The test of the Configurable Logic Blocks of RAM based FPGAs under a Stuck-At fault model has been studied. The high cost of changing the configuration, by reprogramming the FPGA during testing, forces a strategy to reduce the number of different configurations used for testing purposes. After finding the optimal solutions for the elementary structures of the Logic block, Multiplexers and Look-Up Tables, the problem of testing interconnected elementary structures is addressed. The method is illustrated using an elementary structure and then applied to a popular FPGA (XILINX 3000 family) where a reduced set of configurations (5) and their corresponding test sequences is found to cover all (100%) the Configurable Logic Block faults modelled.

Multifunction arithmetic logic units (ALUs) that realize complex arithmetic and logic operations (like the operations of the 74/spl times/181 family) are widely used in today's complex integrated circuits, such as commercial microprocessors and digital signal processors. These ALUs are built around either ripple-carry (RC) adders, carry-lookahead (CLA) adders or mixed CLA/RC adders depending on area and performance requirements. In this paper, first, we introduce novel C-testable multifunction ALUs built around RC adders and linear-testable multifunction ALUs built around CLA adders and mined CLA/RC adders with respect to CFM. Then, we introduce an effective ALU BIST scheme for all three types of ALUs (RC, CLA, mixed CLA/RC) that hits the target of a unified datapath BIST architecture, since it is compatible to an effective BIST scheme for datapaths. Complete CFM testability is achieved with a reasonable number of deterministic test patterns in all cases. The scheme imposes reasonable area overhead and negligible delay overhead and owing to its inherent high regularity can be easily adopted for automatic BIST synthesis of datapaths.

Chips comprising reusable cores, i.e. pre-designed Intellectual Property (IP) blocks, have become an important part of IC-based system design. Using embedded cores enables the design of high-complexity system-chips with densities as high as millions of gates on a single die. The increase in using pre-designed IP cores in system-chips adds to the complexity of test. To test system-chips adequately, test solutions need to be incorporated into individual cores and then the tests from individual cores need to be scheduled and assembled into a chip level test. However with the increased usage of cores from multiple and diverse sources, it is essential to create standard mechanisms to make core test plug-and-play possible. This paper discusses in general the challenges in testing core-based system-chips and describes their corresponding test solutions. It concentrates on the common test requirements and introduces the on-going standardization efforts, specifically under IEEE P1500 Working Group, which is meant to standardize the interface between a core test and its host the System-on-Chip.

This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrated that a set of only 3 Test Configurations called the Orthogonal, the Diagonal-1 and Diagonal-2 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant. Then the test of each configuration is shown equivalent to the test of classical buses. The final proposed Manufacturing Test Procedure present a constant number of Test Configurations (3) and very short Test Sequences.

Datapath architectures are widely used in today's complex integrated circuits, such as commercial microprocessors or specialized digital signal processors. A very effective BIST scheme for general datapaths is introduced in this paper. This scheme requires the register transfer (RT) level description of a datapath design, since it is independent of specific implementations of the functional modules. The novel BIST scheme is generic, i.e. independent of the datapath width. Hence, it is well suited for fixed-width datapaths that suffer from testability problems due to the truncation of the low order half part of multiplications. A simplified version of the scheme can also be applied to non fixed-width datapaths. The deterministic BIST patterns applied, always guarantee more than 99% fault coverage, for the entire datapath, within few hundreds of clock cycles. This result is achieved by exploiting the inherent operational parallelism of datapaths. The scheme imposes small area overhead and near-zero delay overhead.

One of the key factors that has prevented multi-chip modules (MCMs) from gaining mass acceptance in the electronics industry is their high cost. Often contributing to as much as 40% of this cost is the cost of testing the MCMs after they are manufactured. In this paper, we address the problem of testing MCMs fabricated on large area substrates, analogous to the way ICs are manufactured on silicon wafers (this reduces manufacturing cost). Our objective is to reduce the cost of testing MCMs by parallelizing the test process. In this paper we propose a novel relay propagation scheme in which the test stimuli and their correct responses are scanned in an interleaved and pipelined manner into the MCMs. Comparison of the observed and the correct response for each test vector is performed locally at each MCM. It is shown that our scheme results in drastic speedup over conventional boundary scan based testing. We also show that the test time using our testing methodology asymptotically approaches the optimal with the use of larger numbers of test chains.

We address test data compaction for built-in self-test (BIST). The thrust of the work focuses on BIST space compaction, a process increasingly required when a large number of internal circuit nodes need to be monitored during test but where area limitations preclude the association of observation latches for all the monitored nodes. We introduce a general class of space compactors denoted as programmable space compactors (PSCs). Programmability enables highly-effective space compactors to be designed for circuits under test (CUT) subjected to a specific set or test patterns. Circuit-specific information such as the fault-free and expected faulty behavior of a circuit are used to choose PSCs that have better fault coverage and/or lower area costs than the commonly-used parity function. Finding optimal PSCs is a difficult task since the space of possible PSC functions is extremely large and grows exponentially with the number of lines (nodes) to be compacted. We describe an optimization search method based on genetic algorithms for finding combinational PSCs. The factors used to assess the effectiveness of a PSC are its fault coverage and implementation area.

Array multipliers, due to their high regularity, are efficiently designed as parts of complex VLSI devices. Such embedded multipliers have low controllability and observability, making the use of appropriate BIST schemes a necessity. This paper introduces a very effective BIST scheme for carry-propagate and carry-save array multipliers. The deterministic BIST patterns produced by the Test Pattern Generator provide a fault coverage larger than 99%. The required Test Pattern Generator consists of a simple binary counter or maximum length LFSR of a fixed size (8-bits), independent of the size of the multiplier. For Output Data Evaluation a count-based scheme is adopted. The novel BIST scheme does not require any DFT in the multiplier design and is generic, i.e. independent of specific implementations of the multiplier cells.

Booth multipliers are widely used in both general purpose datapath structures and specialized Digital Signal Processors. Such multipliers when embedded in complex ICs have low controllability and observability, so the use of a suitable BIST scheme is a necessity. No Such BIST schemes for Booth multipliers are available to our knowledge in the open literature. A very effective BIST scheme for Booth multipliers is introduced. The algorithmic BIST patterns that this scheme generates guarantee >99% fault coverage. The required Test Pattern Generator consists of a simple fixed-size binary counter or maximum length LFSR, independent of the site of the multiplier. Several count-based compaction schemes are evaluated and a new such compaction scheme is found to be the most effective. The novel BIST scheme is generic, i.e., independent of specific implementations of the multiplier cells and does not require DFT in the multiplier design. Due to its effectiveness and regularity this BIST architecture was adopted for automatic BIST synthesis via the parameterized multiplier generation tool.

This paper presents a new technique for designing reliable multichip modules (MCMs) under radiation effects for spacecraft electronics. The technique is based on current monitoring to detect faults induced by ionizing radiation in dies mounted on the MCM. These faults change transistor electrical parameters and increase power consumption due to increased leakage current. In addition to this fundamental benefit, the proposed approach can also be used to assess product quality during manufacturing testing.

In this paper we look at the results of a yearlong benchmarking effort in the area of IC-level design for testability (DFT). While visiting 10 leading edge companies, we looked at things such as their testability policies, reviews, process for adding testability, their intervals, fault coverage results, and if and where in the system the IC-level self-test was used.

FIFO memories impose special test problems because of their built-in addressing restrictions and access limitations. With the increasing usage of FIFOs today, generic algorithms are needed to test stand-alone FIFO chips and embedded FIFO macros. This paper addresses the problem of testing a very popular type of FIFO, namely the ring-address FIFO. It introduces two novel algorithms to test this type of FIFO. Both algorithms provide full fault coverage for a comprehensive fault model. The first algorithm uses a generic test approach in the sense that it does not require any change to the FIFO hardware. Whereas, the second algorithm is DFT-based. It assumes access to a FIFO design and suggests minor DFT modifications, in order to reduce the test complexity from O(n/sup 2/) to O(n). The BIST architecture of the DFT-based algorithm, which has recently been utilized in different products, is also described.

First-in First-Out memories are becoming increasingly popular as buffer storage between subsystems operating at different data rates. One common way to implement a FIFO is to use a dual-port SRAM memory with a ring-address mechanism consisting of an n-bit shift register (n is the number of words in the FIFO). This saves the address decoder circuitry and allows for higher speed operation, which makes this type of FIFO very popular, especially for embedded applications. The well known functional tests for SRAMs can not be applied to FIFOs because of their built-in access restrictions. Functional fault models and functional tests for Ring-Address Type FIFOs have not been studied and reported before; this paper aims at filling in this gap. It introduces functional fault models and presents a set of tests for Ring-Address Type FIFOs.>

Partial-scan based built-in self-test (PSBIST) is a versatile design for testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage. While PSBIST provides all the benefits of BIST, it incurs less area overhead and performance degradation than full scan. The area overhead is further reduced when the boundary scan cells are reconfigured for BIST usage.>

Faults associated with delays may not cause functional failures at low performance tests. A method to stress macrocells under test, by adding certain delay cells around it, is proposed. Different configurations of delay cells are used to stress delay faults associated with respective paths through the macrocell. An example of the need for this is shown for a macrocell with asynchronous outputs such as an asynchronous-SRAM. This method would detect selected path delay faults, guaranteeing that the SRAM would function in the actual system and not just during test. The delay cells incorporated with the BIST netlist of the macrocell allow the self-testing of such faults during BIST operation.>

BIST is a viable approach to test today's digital systems. Constraints, such as power, noise, area overhead, and others, limit the possibilities of parallel BIST execution in complex VLSI devices. This paper presents a BIST scheduling process that takes into consideration such constraints, and introduces a new BIST control methodology, that implements the BIST schedule with a highly modular architecture. In fact, due to the uniformity of interface, the BIST control elements are independent of the BIST scheme used in the embedded blocks of a device. This BIST control architecture can provide block level diagnostic information.>

A testability strategy that can be implemented mainly by incorporating built-in self-test (BIST) and boundary scan during the chip design cycle is presented. On the basis of these, the testing and diagnosis procedures needed to meet the quality requirements of multichip module (MCM) manufacturing, and hence reaching acceptable MCM assembly yields is demonstrated. The proposed testability strategy can be considered universal, since it is independent of silicon, substrate, or attachment technologies adopted to build the MCM.>

A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small likelihood of error escape (aliasing) is described. For test generation, the scheme uses the exhaustive test technique. For output data evaluation the scheme uses both time and space compactors. Linear space compaction is performed using a multiple-input linear feedback shift register (MISR). For time compaction, nonlinear compaction (count-based) enhanced by the output data modification (ODM) technique is used. Space compaction is further enhanced by using a bidirectional MISR.>

The authors present a unified probabilistic model of count-based compaction that relates the probability of occurrence of the counted events to a circuit's fault detection probabilities. This model allows an identical treatment of all the different count-based techniques proposed to date, e.g. ones, transitions, edges, and spectral coefficients, by essentially reducing all techniques to simple ones-counting. From a Markov model of ones-counting, the authors derive asymptotic aliasing probabilities, and for finite test sequence lengths they developed a computation technique for determining the aliasing associated with the specifically mentioned schemes, as well as more general count-based compaction techniques, under various error models.>

A unified probabilistic model of count-based compaction is presented that relates the probability of occurrence of the 'counted' events to a circuit's fault detection probabilities. This model enables an identical treatment to be made of all the different count-based techniques proposed to date, e.g., ones, transitions, edges, and spectral coefficients. Based on this model, the authors propose a computation technique for determining the error escape associated with these specific, as well as more general, count-based compaction techniques, under various error models.>

The authors propose a novel BIST (built-in self-test) scheme for ROMs that has an extremely low possibility of error escape. The scheme is referred to as exhaustive enhanced output data modification (EEODM). For the test generation. EEODM uses the exhaustive test technique. This guarantees the complete coverage of all combinational faults in the ROM. For output data compaction, EEODM uses an enhanced form of output data modification (ODM), along with bidirectional polynomial division. The hardware and test-time overhead was compared with that associated with other known BIST schemes. EEODM turns out to be very attractive, since it achieves much higher fault coverage than any of the other known schemes, and yet the associated overhead is very reasonable.>

A unified solution to the problems that arise in the design, development, and test of VLSI processors is offered. The JTAG/IEEE P1149.1 standard boundary-scan architecture is proposed as the basis for designing testable, defect-tolerant, VLSI processors. The test access port (TAP) provided by the boundary-scan architecture is used to control and repair the microprogram control unit, as well as to control and observe key control and data values. Built-in self-test and boundary-scan are used to solve other test problems. The TAP is also used to provide a measure of defect tolerance.>