This paper proposes a novel redundancy-based approach to drastically relax the matching requirements of CDACs and employing a cost-effective digital calibration method to improve linearity. The proposed architecture features a 3-segment CDAC with two redundant bits, which effectively reduces the overall DAC area and improves the DAC’s linearity. A 15-bit version of the DAC has been implemented in TSMC 0.18 μm technology, occupying a total area of 0.010 mm2. The design is validated through simulations in Cadence Spectre and calibration in MATLAB, resulting in worst-case integral nonlinearity (INL) and differential nonlinearity (DNL) of less than 0.5 LSB and 1 LSB, respectively, across 200 Monte-Carlo iterations.

This tutorial paper discusses an efficient approach that can be adopted to analyze complex analog circuits. The approach is specifically designed to show the graphical interdependencies between system nodes and variables and has been validated across multiple engineering disciplines. By utilizing this graphical approach, we reduce the dependency on circuit analysis techniques that often requires solving extensive systems of simultaneous equations as while effective, they become increasingly difficult and error-prone when applied to circuit with numerous voltage nodes. This paper presents an alternative approach that utilizes basic small-signal analysis principles, Gain Formula from control theory to derive the transfer functions of the circuit or its sub-circuits. The method simplifies the analysis process by directly providing closed-form expressions for the transfer function. This approach not only reduces the general difficulty of the circuit analysis but also minimizes the potential for algebraic mistakes, which are common when working with analytical techniques. Furthermore, it removes the guesswork typically involved in the simplification process found in many textbook examples, where assumptions or approximations are often employed to simplify complex circuits.

The rising demand for defect-free integrated circuits (ICs), especially in the mission-critical automotive industry, has stimulated the development of more efficient defect detection methods. Currently, defect testing methods for digital circuits are far more advanced than for analog circuits, largely due to the greater functional complexity of analog designs. However, in the automotive industry, almost 80% of IC failures stem from defects in analog circuits, creating an urgent need for robust and cost-effective defect detection techniques for analog and mixed-signal (AMS) circuits. This paper presents an all-digital defect detection approach for charge-pump phase-locked loops (CP-PLLs). The proposed Design for Test (DFT) strategy harnesses the robustness of digital control and monitoring circuits to improve detection accuracy, minimizing false failures. Through extensive transistor-level simulations, we demonstrate that the proposed method achieves a high defect coverage of over 97.5% with minimal chip area (< 0.1%) requirements for the BIST circuits.

High-resolution waveform generation is essential for Built-In Self-Test (BIST) and biomedical applications, where signal integrity is crucial. Traditional approaches rely on expensive Automated Test Equipment (ATE), highlighting the need for cost-effective alternatives. This paper presents a cheap approach for generating a 24-bit waveform using two low-cost 14-bit DACs enhanced with dithering to achieve high purity. A 14-bit ADC is employed as both the measurement device and, when needed, the Device Under Test (DUT) using the generated signal. Measurement results show that we achieve a signal with an Effective Number of Bits (ENOB) of 21 bits and distortions exceeding 130 dB, confirming the effectiveness of the design. The proposed approach provides a high-precision, cost-effective solution for embedded systems that require accurate signal generation, particularly for precision analog and mixed-signal (AMS) testing.

In this brief, we present the development of an on-chip sensor designed to monitor hot-carrier-induced (HCI) aging in NMOS transistors, utilizing the hot-carrier-induced series-resistance enhancement (HISREM) model. With a 10 MHz clock and SAR logic, the sensor generates a digital output proportional to device age under HCI stress, achieving 8-bit accuracy. Our methodology was developed using GF22FDSOI technology and evaluated over a 20-year period with extensive Cadence RelXpert simulations. We validate the sensors’ robustness to process variations and random mismatches through 200 Monte Carlo (MC) iterations. INL and DNL evaluation is used to ensure that the accuracy of the design is sufficient even in the worst-case corner conditions.

Testing high-resolution Digital-to-Analog Converters (DACs) often requires costly equipment, such as Automated Test Equipment (ATE) or high-resolution Analog-to-Digital Converters (ADCs). This paper presents a Built-In Self-Test (BIST) approach for high-resolution DACs, leveraging a 14-bit ADC to effectively test a 20-bit DAC. By embedding this solution within the DAC design, the proposed approach achieves scalability and significantly reduces test costs while maintaining good linearity and dynamic performance. The approach is validated through simulation results of the 20-bit DAC designed in GF22nm FDSOI technology and the BIST scheme modeled and validated using MATLAB. Results from 100 Monte Carlo simulations validate the robustness of the proposed testing scheme, achieving an INL estimation error of less than 0.4 LSBs.

This article presents a systematic approach to generate layouts for two devices, with an arbitrary integer ratio of device sizes, that cancels up to at least third-order gradient effects. A new analysis leads to mathematical constraints on 1-D layouts that meet the required integer ratio and cancel second-order gradients. From those layouts, we apply reflection and rotation symmetries to generate 2-D layouts that cancel higher-order gradients. We demonstrate our proposed methodology on current sense transistors interspersed in active power transistors. Legato electrothermal simulation show our proposed approach, respectively, improves worst-case matching accuracy about a factor of 9.9 and 7.15 when compared to a common centroid (CC) and interdigitated (ID) pattern in the presence of gradients effects. Furthermore, we discuss evaluation metrics that can be used to select one of multiple gradient canceling layouts for any fixed rectangular grid and device application.

Bias Temperature Instability(BTI) is an aging phenomenon in MOS transistors which is increasingly becoming one of the critical concerns for reliability of analog, digital and mixed-signal circuits, especially in deeply scaled technologies. This paper presents a robust integrated sensor that allows for the direct monitoring of the BTI-induced threshold voltage change of MOS transistors that have been subjected to stress. We achieve this by comparing a MOS transistor or device-under-test(DUT) which is stressed and is likely to suffer from BTI aging with a reference MOS device for which measures have been taken to ensure that it experiences negligible aging during its lifetime. The mixed-signal nature of the proposed sensor architecture allows for a direct physical-to-digital conversion of the BTI-induced threshold voltage change, as well as, fast measurements which is crucial because of the recovery effects of BTI. We also discuss a potential use case of proposed sensor for the online monitoring of an analog circuit.

This paper presents a resistorless curvature-compensated bandgap voltage reference (BGR). The proposed method, using ratioed transistors and the inverse function technique, attempts to extract VGO, the bandgap voltage of silicon, by canceling out both the T and TlnT terms in the temperature characteristic of the bipolar junction transistor's (BJT) base-emitter voltage, VBE. The proposed design is implemented in the TSMC 180nm process. Simulation results show that the circuit can achieve temperature coefficients (TC) of less than 4.7ppm/°C from −20°C to 80°C over process variation and mismatch.

A strategy for designing a high accuracy voltage reference operating at sub 1ppm/°C over a wide temperature range is introduced. The proposed design makes use of one of the popular and widely used bandgap voltage reference structures and the temperature dependence of the drain current of a single MOS transistor operating in subthreshold to build a sub-ppm/°C voltage reference. The effects of error sources which may affect the performance of the voltage reference are analyzed and minimized. Simulation results in the TSMC 180nm process show that the design can achieve temperature coefficients of less than 0.85ppm/°C across process corners and local random variations from −40°C to 125°C after trimming.

This paper describes a low-cost technique for extracting parameters of interest for test boards used in multisite automatic test equipment (ATE). In the proposed approach, physical elements and nets on the PCB are represented as a graph with nodes and edges. Graph traversal algorithms are then used to extract data about the connections between specific components on each test site. This approach automates the previously slow and manual process of generating the topology files necessary to extract board parameters. The proposed method is implemented on a multisite test board, and results are presented.

Backed by standards like ISO26262, achieving near 100% defect coverage is becoming a common reliability requirement in the ever-growing automotive industry. However, achieving high defect coverage in an analog circuit has been proven to be a difficult/expensive task even with sophisticated analog and digital testing circuitry. In this work, we present a simple design for testability (DfT) technique that achieves 98% defect coverage for operational amplifiers including Widlar current reference and biasing circuitry. Our robust testing method utilizes purely digital testing circuits and is extremely time-efficient reducing the test cost. The proposed method can be used both at production test and for on-line health monitoring post-deployment to detect zero-time and latent defects. Also, the digital nature of our method presents a way for defect localization through the recorded bit streams. In this work, we also introduce a simple method to detect defects in the Widlar current reference and the bias current circuit. We validate all our results using extensive transistor-level simulations in UMC65nm technology.

Hardware security vulnerabilities to hardware Trojans in widely used filter structures are identified. The widely used two-integrator loop filter architecture known as the Kerwin-Huelsman-Newcomb (KHN) Biquad is used to demonstrate the vulnerability. It is shown that the relationship between the passive component values and the nonlinear amplifier parameters, the slew rate and the output saturation voltages, determine the presence or absence of a stationary nonlinear undesired oscillatory mode of operation. Experimental results obtained from a discrete component filter demonstrate the vulnerability to the Trojan mode of operation in this filter structure.

Level shifters form an indispensable part of modern system on chips (SoCs) with their use encompassing multi-VDD logic designs [1], voltage stacking designs[2] and high voltage designs[3]. Traditionally, level shifters have been characterized using energy-delay curves (or correspondingly the energy-delay product) [2]. All the aforementioned applications provide the level shifter’s higher supply voltage through an external pin. Also, the primary objective in the previously mentioned applications has been reduction in energy consumption. Thus, energy-delay product is an appropriate figure-of merit (FOM) for these applications. However, unlike these applications certain analog/mixed signal(AMS) applications like that in [4] employ charge-pumps to generate the higher supply voltages. The FOM of energy-delay product is no longer appropriate in these cases for two reasons. First, the use of energy delay curves to characterize and choose the appropriate level shifter architecture ignores the energy consumed by the charge pumps to generate the higher voltages and can eventually lead to an overall larger energy consumption. Secondly, since the current from the higher voltage is provided through a charge reservoir (capacitor in most cases), voltage droop during switching should also be accounted by the FOM. Optimizing the energy-delay product does not account for this effect. We therefore argue that charge-delay product (or correspondingly the charge-delay curves) is a better FOM to compare level shifters to be used in such applications. The “charge” of concern here refers to the charge consumed through the higher supply voltage. One might argue that charge-delay optimization is equivalent to energy-delay optimization. However, we would like to emphasize the fact that our objective is to obtain the optimization between the charge consumed from the higher supply voltage and the delay of the level shifter. This FOM allows for trading off higher energy consumption from the lower supply voltage for a lower charge consumption from the higher supply voltage.

This paper presents a simple, low-cost temperature-to-digital-converter (TDC) with a wide operation range of $-55 ^{\circ}\text{C}$ to $200 ^{\circ}\text{C}$ and inaccuracy of $\pm 1.9 ^{\circ}\text{C}$. The proposed method relies on device and layout matching to cancel the effects of component temperature coefficients and I-V characteristic nonlinearities and to enable accurate temperature sensing. Additionally, the proposed method decreases the design complexity and significantly improves area requirements and conversion speed of the TDC. Moreover, in the proposed design, no complicated signal processing devices, such as analog-to-digital converters (ADCs), are used, further decreasing the cost in terms of area and energy per conversion. The design is implemented in 65nm CMOS technology with a supply voltage of 2.5V. The total area of this TDC is 0.007 mm $^{\mathbf{2}}$ with an ultra-low energy per conversion of 9nJ.

The number of electronic components in mission-critical applications is increasing rapidly and, with the dawn of electric vehicles, this increase is expected to accelerate in the near future. As functional safety (FuSa) is of utmost importance in these applications, the increasing demand for integrated circuits with zero defective parts per million (DPPM) is pressing the chip industry to achieve high defect coverage. In this paper, simple digital Design for Test (DfT) techniques are presented to detect defects in Low Drop-Out Regulators (LDO). The proposed method uses digital mismatch injection and digital-like detectors to detect various defects in an LDO. The digital nature of the proposed method can help reduce the test cost by avoiding expensive and time-consuming analog testing circuitry. Using spice simulations, we show that our method can detect up to 97.5% of the defects providing high defect-coverage. Additionally, as our injectors and detectors are simple in nature, they are not only area-efficient and easy-to-design but also easily scalable. Furthermore, in this work, we also introduce a simple and robust dual-threshold detector that can be used to monitor faults in biasing circuits.

On-chip testing for analog/mixed signal circuits helps improve reliability of safety-critical systems by enabling infield testing. It also alleviates the problems of increasing test costs. A low-cost high accuracy stimulus generator for on-chip spectral testing is proposed. The generator uses a low-cost DAC which requires minimal design and re-engineering efforts, in conjunction with INL based digital pre-distortion to calibrate its linearity performance. DAC output measurement, DAC INL estimation and DAC linearity calibration are all performed on-chip. Measurement results in 40nm bulk CMOS technology demonstrate that the circuit is capable of producing a rail-to-rail differential signal with THD of -75 dB and SFDR of 79dB. The proposed solution is a major step forward in demonstrating the feasibility of synthesizable built-in-test solutions for high-accuracy embedded analog and mixed signal functions.

Multisite (parallel) testing is becoming more widely used in analog and mixed-signal testing to increase throughput and meet high customer demand. However, site-to-site variations are inevitable due to the complexities involved in massive multisite test board design. Sites with pronounced systematic errors (issue sites) lead to measurements not reflecting the true performance of the device under test (DUT), causing potential yield loss and test escapes. Traditional mechanical repair of such sites is expensive, time-consuming, and labor-intensive. Polynomial transformation methods have been successfully explored to calibrate measurements at issue test sites. However, its rigid application could lead to overfitting or underfitting without foreknowledge of the nature and level of induced errors. This paper presents an optimal order polynomial transformation method that is flexible and self-adaptive. It uses a predefined error metric to find the optimal-order of the transformation polynomial and provides optimal calibration coefficients. Simulations and real test data are used to evaluate the effectiveness of the proposed method. Further validation is also provided by comparing the die measurements of issue sites after calibration against a more accurate reference.

The multisite test hardware is built with imperfect elements. Hence, like all measuring instruments, measurement errors are induced by test sites. These errors (random and systematic) are usually insignificant to guarantee test quality. However, as the number of test sites on the multisite tester increases (to further increase throughput), the induced systematic errors for some test sites become pronounced. The measurements of some test sites no longer reflect the true performance of the device under test (DUT), and the likelihood of yield loss or potential test escapes is increased. While multisite test hardware troubleshooting and correction can be difficult, time-consuming, and expensive, it is much easier to calibrate the measurements of issue sites (test sites with unacceptable systematic variations). This paper proposes a least-squares method for systematic hardware error identification and calibration. This method uses linear regression to compare the distribution of measurements at each test site to that of a reference (true and expected) distribution as a means to identify systematic errors and calibrate them. This approach provides a practical black box technique to mitigate test hardware systematic variations and further guarantee test quality. MATLAB® experiments indicate our approach outperforms existing methods in terms of accuracy. Application of the method to real test data confirms the effectiveness and robustness of the method without compromising test quality.

This paper proposes a novel method for a structural test of the Successive Approximate Register (SAR) Analog to Digital Converter (ADC). The presented strategy has an ignorable area and power overhead and is implemented entirely digitally. We introduce simple digital checkers for the structural test of the sample and hold switch. Moreover, with no addition of extra circuitry and using the normal potential of the ADC we will perform a fast and localized fault detection for the heart of the ADC, capacitive DAC block. The BIST can be applicable as both post-production and in-field tests, capable of detecting zero-time defects and latent defects. The proposed BIST has zero to none area overhead, fast run time, 100% coverage, and is fully digital with no degradation of the normal operation and performance of the ADC.

Multisite testing has become a proven method to reduce test time and costs for integrated circuits (IC). However, the technique suffers from site-to-site variations, especially when a large number of test sites are involved. It becomes imperative to identify issue sites that exhibit unacceptable variations to prevent yield loss or incorrect passing of faulty devices. By correctly identifying the true probability distribution of tested specifications, identification of issue sites becomes easier. We introduce an ordinal optimization-based algorithm to select the right sites to estimate the true distribution in situations where it is difficult or impossible to find the true distribution for tested specifications. Using both simulation and real-world ATE test data, we demonstrate that this approach yields good results.

Multisite testing significantly increases throughput by testing multiple chips simultaneously. When implemented on a large scale (massive multisite), the complex signal routing involved, interference, and coupling on the test hardware (amongst other issues) often affect test sites differently, introducing variations in site measurements. We hypothesize in this paper that each test site’s measurement can be modeled as a weak nonlinear function of the true chip measurement with systematic errors. We propose an algorithm to detect these systematic errors and calibrate them. This approach provides a practical black box technique to mitigate test hardware variations while investigating the fundamental root causes. The proposed method is verified with simulation and real test data.

A general approach based on a natural basis function expansion to cancel the temperature-curvature of the base-emitter voltage in the bipolar transistors embedded in bandgap references is presented. The proposed method can be applied to the widely used Banba, Kuijk, and Brokaw structures to build references with sub-ppm/°C temperature coefficients. Current version and voltage version embodiments based on a self-bootstrapping concept are provided. Error sources that can potentially affect the reference performance are analyzed and their effects on the temperature coefficient are minimized after trimming. Monte Carlo simulation results confirm that after calibration, temperature drift performance is within the design/trimming target 0.5 ppm/°C. A partially integrated Kuijk-based prototype reference has been designed and fabricated in a 65nm UMC process. Measurement results demonstrated a 1.5 ppm/°C temperature coefficient over a temperature range of 0 °C to 80 °C with a low-cost two-temperature trimming method. With additional trimming, 0.8 ppm/°C performance was achieved.

This paper presents a simple structure to extract VGO, the silicon bandgap voltage at zero Kelvin. Based on a traditional Kuijk structure, a third diode with a temperature constant current is used to extract the curvature TlnT term. A novel Gm cell-based voltage summer is proposed to perform the curvature correction. A single temperature trimming method is implemented to trim out PTAT errors and calibrate the gain of the summer. The bandgap reference circuit is simulated in the UMC 65nm process. With the proposed trimming method, a temperature coefficient less than 10 ppm/°C from -40 °C to 125 °C can be achieved.

This paper presents an analog duty cycle corrector with feedback. A differential charge pump with fast startup is used to detect the duty cycle error and outputs a control voltage for current-starved inverters to adjust the pulse width. The pump current is designed to be adaptive to the input frequency, so a wide frequency range is achieved without requiring a large load capacitor. The circuit is designed in a 130nm CMOS process and can correct 4-100 MHz clocks with 25-75% duty cycle range. The simulation results show that output error is limited to 1.5% and the power consumption is 50 μW at 100 MHz.

An operational amplifier (op amp) is a fundamental block used extensively both as a stand-alone device and as a major block embedded in an SoC. To fully characterize an op amp, sophisticated analog and digital testing is required, which is expensive. Fault detection techniques have proved to reduce package cost and test cost by detecting faulty devices early in the test sequence. In this paper, a simple Design for Test (DfT) technique called intentional offset injection is proposed to detect various faults in the op amp. As our proposed method is completely digital, pure digital circuitry can be used, thereby avoiding expensive analog testing. The op amp can be tested with the proposed fault detection method during wafer probe test right after the continuity tests and the faulty devices could be discarded, thereby circumventing time-consuming analog testing. Additionally, our detection scheme can be used for power-on selftest after deployment and for online health monitoring during normal operation. We show that the proposed detection method can provide high fault coverage of 95% with modest area requirements. In this work, we also introduce a detector called digital window comparator which is used to monitor faults in the biasing circuit as well as in the Widlar current reference providing increased fault coverage.

Multi-site testing saves test time and tests cost by screening multiple chips at once. However, it comes with its issues. As test engineers increase the number of sites on each tester to further save test time and cost, variations are now being observed in measurements from site to site which do not correspond to actual problems in the devices under test. Thus, a cost-effective way to investigate site to site variations and identify sites with issues needs to be developed to ensure high test quality and to rule out possible problems arising from the test hardware. In this paper, regression fitting on a quantile-quantile curve is used to compare the distribution of each site to a theoretical and expected distribution. This is shown to pronounce site to site variations inherent in test data, hence identifying issue-ridden sites with ease. The quantile-quantile plot compares the integrals of two probability density functions in a single plot, thus capturing the location, scale, and skewness of the test data set. This method provides more information to the test engineer than classical statistical methods that rely on single test statistics for distribution comparison and is at no extra cost.

This paper presents a general approach to extract VGOfrom the base emitter voltage of a bipolar transistor. VGOis the silicon bandgap voltage at zero Kelvin and it is a physical constant voltage independent of temperature. The proposed method can be implemented on any of the widely used Banba, Kuijk, Brokaw or resistorless structures to build voltage references with sub-ppm/°C temperature coefficient. One embodiment based on Kuijk structure is used to illustrate how the proposed VGOextraction can be realized. Error sources which can affect the voltage reference's performance are analyzed with a new base expansion and their effects on the temperature coefficient are minimized after the proposed two-temperature trimming. Transistor level simulations are run in GlobalFoundries 130nm process and simulation results show that the design can achieve 0.5 ppm/°C temperature coefficient from -40 °C to 125 °C.

Analog-to-digital converters (ADC) are one of the most important components in modern electronic systems. In the mission-critical applications such as automotive, the reliability of the ADC is critical as the ADC impacts the system level performance. Due to the aging effect and environmental changes, the performance of the ADC may degrade and even fail to meet the accuracy requirement over time. Built-in self-test (BIST) and self-calibration are becoming the ultimate solution to achieve lifetime reliability. In this paper, two ADC testing algorithms and two ADC BIST circuit implementations are developed and validated.

Multi-tone test is critical in evaluating the overall spectral performance of integrated circuits, especially when the whole signal bandwidth is filled with various frequency components. Coherent sampling is a major challenge for achieving accurate test results in multi-tone test, because it is difficult to simultaneously control all the signal tones precisely. Once coherent sampling is not satisfied, the spectral leakages and their overlap effect will deteriorate the spectral test results. In this paper, a new algorithm is proposed to eliminate the requirement of coherent sampling in multi-tone test. In this method, all the tones are simultaneously estimated with a two-step method which employs merely two FFTs and a few simply mathematical operations. Then new coherent data is reconstructed by replacing the noncoherent fundamentals with coherent tones, all the spectral leakages are removed. Extensive simulation results demonstrate that the proposed method can achieve the same testing accuracy as coherent sampling methods in arbitrary level of noncoherency. The proposed method greatly relaxes the test setup for multi-tone test, and hence the test cost can be reduced significantly.

Timing jitter is a crucial factor for high speed and high performance ADCs. Random clock jitter and the intrinsic aperture jitter of the ADC raise the noise floor and make it difficult to accurately estimate ADC specifications from the output spectrum. The stringent requirement of coherent sampling imposes further constraints on the test equipment. The proposed method significantly relaxes clock jitter and coherent sampling requirements by utilizing a dual channel test setup. The algorithm can efficiently separate and estimate noise, intrinsic ADC aperture jitter and random clock jitter, while allowing for arbitrary non-coherency in sampling. Simulation results of ADCs of different resolutions and sub-picosecond jitter levels validate the functionality and accuracy of the method.

This paper presents a Concurrent Sampling (CS) method for measuring a multitude of analog DC voltages concurrently using local digitization. Boolean results after digitization are routed in an IJTAG compatible fashion. Analog quantities are no longer routed across the die, thus overcoming several limitations of Analog Test Buses. Furthermore, the proposed method enables real-time measurement of analog voltages, thus addressing a growing need for Automotive test and reliability. The proposed method is applied to an analog circuit consisting of widely used analog blocks such as a bandgap reference and an operational amplifier. Transistor level simulation results demonstrate that the proposed method is functional and the drawbacks of the ATB are no longer present.

A fully integrated low-dropout regulator (LDO) with ultra-fast transient settling is proposed to provide a clean supply for digital circuits in nano-scale technology. A super source follower (SSF) is inserted into the cascode flipped voltage follower (FVF) topology to drive the power transistor for fast turn-on. The proposed positive transient detection (PTD) circuit drive a NMOS transistor for fast pull-down. The combined effects of these two techniques significantly attenuate the load transient induced voltage spikes. The LDO is designed in a 130 nm CMOS process and consumes 100 μA quiescent current with 1.2 V regulated output and 200 mV dropout voltage. For large load transient of 100 μA to 20 mA and back to 100 μA, the simulated undershoot and overshoot is less than 95 mV with 150 ns recovery time, demonstrating a glitch peak reduction of 6 times and a glitch settling time reduction of 5 times.

Built-in self-test(BIST) for AMS circuit is widely investigated and developed in the last decade since it is a promising alternative to traditional testing. In particular, SEIR (stimulus error identification and removal) based BIST circuit has been proved to be a cost effective and practical ADC BIST solution for ADC testing. The SEIR method can relax the linearity requirement of input signal for ADC. However, high constancy of level shift between two signals are needed for testing high resolution ADC's linearity. This paper presents a new method to introduce the highly constant level shift and a new structure of output buffer with true rail-to-rail performance without degrading close-loop gain by applying correlated level shifting (CLS)technique. The simulation results show that the constancy of level shift is only 2.2ppm over the entire ADC input range. The constancy level is able to test 18 bit ADC to 18 bit accuracy level for full-codes testing.

A transparent side channel trigger mechanism triggering Power/Area/Architecture and Signature Transparent (PAAST) analog hardware Trojans is discussed in this paper. By applying this trigger mechanism through normal supply bus, the circuit can be triggered to the Trojan state. Same as the stealth nature of PAAST Trojans, it doesn't require any additional area, any additional power, any structure modifications and it doesn't leave any signatures in either power domains or signal paths. This trigger mechanism can be applied on circuits with static Trojans or circuits with dynamic Trojans.

Analog-to-Digital Converters (ADCs) are among one of the world's largest volume devices. ADCs are a necessary, vital mixed-signal integrated circuit (IC) component in almost every electrical device and system. One of the challenge is to accurately and cost-effectively test the continually better performance ADCs. For spectral testing of the ADC, one of the goals is to obtain dynamic performance of the ADC under test. The conventional test has become extremely difficult to implement accurately and cost-effectively, since the test stimulus to the ADC must have an even better purity than ADC under test with continuously higher performance. In addition, multi-tone tests require harmonics and spur, as well as the intermodulation must be accurately tested without influence from impure test stimuli. To resolve this issue, this paper proposes a new method. This method uses the low purity test stimulus instead of a high precision test stimulus, passes the signal to two different cost-effective filters, and the output signals are then sampled by the ADC, by separating the nonlinearity from the source, the true ADC nonlinearity is accurately estimated. And the dynamic performance of the ADC under test can be obtained. Extensive simulation results validate the functionality and robustness of the proposed method with different levels of impure test stimulus and different types or resolutions of the ADC under test. The proposed method greatly reduces the requirements on the test stimulus and is implemented into the board level or on-chip high performance ADC spectral testing and characterization.

Sine waves are among the most widely used signals in many applications such as signal and device testing, measurement, communications, medical electronics, consumer electronics, etc. The high purity sine wave is crucial, as it is needed for high precision applications. Such high purity signals have become more challenging to generate, as the devices under test such as Analog-to-Digital Converters (ADCs) performances are becoming better, which the test signals need to have even better performances. This paper presents a cost-effective method to generate high purity sine waves using a nonlinear DAC. Based on a novel method that identifies the DAC nonlinearity, such information is fed back to the DAC input codes, cancels its nonlinearity, and results in a much better purity sine wave output. In addition, both linearity information of the DAC and ADC used can be accurately tested, which can be used for co-testing of the DAC and ADC. Extensive simulation results have verified the functionality and robustness of the proposed method, with different performances, structures or resolutions of the DACs and ADCs. The proposed method and system can be implemented on board or on chip that serves high performance high precision applications, with much lower design requirement and cost.

Production test of parametric specifications is a significant contributor to the overall cost of build for analog and mixed-signal products. Data converters (ADCs and DACs) in particular are critical components of integrated circuits used in control/actuation and sensing applications. If left un-optimized, their production test time often dominates the overall system-on-chip (SoC) test time. In this paper, we specifically focus on static linearity test of DACs and propose architecture-aware test methods that are combined with best-in-class fast linearity test concepts in the literature to minimize test time without compromising test quality. The proposed methods exploit the hypothesis that the number of device errors which contribute to linearity errors can be captured by a significantly fewer number of variables than the number of codes at which linearity needs to be tested. We introduce a new time and memory efficient method called Extrapolated Reconstruction (ER) to calculate DAC INL and DNL, based on the segmented model introduced in uSMILE. We also demonstrate that since the segmented model techniques do not account for interpolation, they are not suitable for interpolated DACs. We thus develop an interpolated segmented model and enhance both uSMILE and ER to obtain two new methods that provide correct estimations for interpolated DACs. A linearity test time reduction of 15×-20× was seen in actual silicon measurement results for multiple 12-bit DACs and >100× was seen in simulation case studies for many 16-bit DACs.

This paper presents a precision voltage reference generator targeting sub-ppm temperature coefficient over a wide temperature range. Unlike conventional curvature correction techniques that attempt to cancel the temperature nonlinearity of Vbe, the proposed method is specifically targeted at extracting Vgo from the temperature characteristic of Vbe. Vgo is the band gap voltage of silicon extrapolated at zero Kevin and is temperature independent over a very wide temperature range. Analytical constraints are carefully investigated that lead to strategies for creating an output voltage that is proportional to Vgo when certain mismatches and offsets are accurately trimmed. The proposed method is implemented in the GlobalFoundries 130nm process. Simulation results show that the design can achieve temperature coefficients as low as 0.7ppm/°C from -40°C to 125°C over process corners.

This paper presents a clock-less digital pulse stretcher which takes a short pulse as input and produces a detectable pulse that is longer than a required minimum duration. The proposed structure has high sensitivity to input pulse width and height and is capable of detecting deep sub-nanosecond pulses. This enables a wide variety of applications ranging from characterization of radiation-induced single-event transients to detection of glitch attacks and tamper resistance for security. Implementation of the proposed pulse stretcher in a 130nm process validates the analytical relationships between the input and output pulse. Simulation results show that the design can capture an input pulse with width larger than 50ps and height greater than 300mV. The shortest pulse that can be detected by the design can readily scale down with technology due to the digital nature of the circuitry.

Spectral testing has become one of the most widely used approach to characterize electronic systems. As the performance of the system becomes higher, the cost and the difficulty of accurately characterizing such systems has increased dramatically. To obtain accurate spectral results of signals from such high performance systems, one of the stringent test requirement is to maintain stable signal amplitude. If such requirement is not met, spectrum leakage will show up at the spectrum and the correct signal spectral performance cannot be obtained. In this paper, a low-cost method is proposed to estimate and remove amplitude drift in the signal under test, via segmentation and Least Square, and accurate spectral testing results of the signal can therefore be obtained. Extensive simulation results demonstrated the accuracy, as well as the robustness of the proposed method, which is capable of obtaining accurate spectral performance of the signal under various test conditions. Such low-cost method relaxes the stringent requirement such as constant amplitude on the signals under test, and can be implemented for high precision spectral testing using less precise instrumentations.

This paper presents a complete on-chip ADC BIST solution based on a segmented stimulus error identification algorithm known as USER-SMILE. By adapting the algorithm for efficient hardware realization, the solution is implemented towards a 1Msps 12-bit SAR ADC on a 28nm CMOS automotive microcontroller. While sufficient test accuracy is demonstrated, the solution is further extended to correct linearity errors of ADC. The entire BIST and calibration circuitry occupies 0.028mm2silicon area while enabling more than 10 times tester time reduction and >10dB THD/SFDR performance improvement over an existing structural capacitor-weight-identification calibration scheme. The added die cost is estimated to be 1/8 of the saved test cost from tester time reduction alone.

Spectral testing and linearity testing are two important categories in ADC testing. The sampling clock quality is a crucial factor in ADC spectral testing. The cumulative clock jitter of the sampling clock generates power leakage in the fundamental component of the ADC output spectrum, and the random clock jitter increases the noise floor of the ADC output spectrum, which corrupts the spectrum result of the ADC. This paper proposes a new algorithm to accurately estimate the ADC specifications despite sampling clock jitter. The ADC output sequence is divided into small segments. Each segment is paired with another one, such that their initial phases match with each other the best. By analyzing the difference of each segment pair, the noise power is separated from clock jitter and is estimated accurately. In each segment, by removing the estimated local cumulative jitter, the leakage due to cumulative clock jitter is removed, correct harmonic and non-harmonic spur information is obtained. Simulation and measurement results comparing with the standard test methods corroborated the accuracy and robustness of the new solution. This method significantly relaxed the stringent test requirements on high precision sampling clock and dramatically reduced the test cost and complexity, which offers potential for low cost on-chip testing.

Analog-to-Digital Converters (ADCs) are becoming increasingly common to be involved in most systems in Integrated Circuits (ICs). Thanks to the rapid growth of modern semiconductor technology, the performance of the data converters becomes better and better. One of the difficulties being faced is to be able to accurately and cost-effectively test the continually better performance ADCs. The conventional test method for ADCs can be difficult to implement accurately and cost effectively due to the stringent requirements, such as achieving coherent sampling, requiring high purity test stimulus, avoiding signal clipping, maintaining stationary test environment and minimizing clock jitter. To relax these necessary conditions and to reduce test cost while achieving high accuracy, several new algorithms are introduced in this paper, to perform accurate spectral and linearity test of the ADC without requiring precise test instruments. Extensive simulation results performed in MATLAB first validated the accuracy as well as robustness of the proposed algorithms. Furthermore, measurement results using different devices and test platforms have verified many of these algorithms. For the first time, the accurate testing can be performed without the need for stringent requirements of conventional test, which offers much more flexibility as well as lower cost. Combined with their easy, cost-effective setup and high accuracy, these algorithms are readily available for precision ADC characterization and can be implemented into Built-in-Self-Test (BIST). solutions for production and bench testing.

A method for separating and accurately estimating ADC noise, aperture jitter, and clock jitter is presented for ADC testing and characterization. This significantly relaxes clock jitter requirements and removes the need for high precision test instruments, but still allows ADC specifications like SNR, SNDR and ENOB to be accurately estimated.

Jitter performance plays a crucial role in bit-error-rate of a high-speed digital communication system. Jitter decomposition is a key tool to accurately derive each type of jitter as well as total jitter in a system and identify the root causes of jitter. In this paper, we propose a jitter decomposition algorithm using least squares (LS) which simultaneously separates inter-symbol interference (ISI), random Jitter (RJ) and periodic Jitter (PJ). The algorithm includes a new time domain ISI model based on channel pulse response which is more effective than a conventional cursor convolution technique. The proposed jitter decomposition method is able to obtain the estimated individual jitter component value with great accuracy by using fewer samples of total jitter data compared with conventional methods. The simulation and hardware experiment demonstrate the efficiency and accuracy of the proposed method.

The ultrafast segmented model identification of linearity error (uSMILE) algorithm dramatically reduces ADC linearity test time while achieving superior test accuracy. This method avoids the gross inefficiencies in the conventional histogram test method to reduce the test data by a factor of over 100. However, in low noise environment where the quantization noise becomes dominant, uSMILE leads to large (up to +/-0.5 LSB) INL estimation error. In this case, proper extra noise needs to be added to the stimulus in order to whiten the quantization noise. In this paper, a pseudo random dithering method and a low-cost implementation of dithering generator in SAR ADC are proposed. The random pattern is generated from a simple shift register and XOR gate. The dithering is added through the dummy capacitor of SAR ADC during the ADC sampling phase. The proposed scheme is validated through extensive simulations. The maximum INL estimation error in a 12-bit ADC with 1 hit/code ramp test is within ± 0.1LSB.

A systematic method is proposed to approach complete fault coverage for catastrophic faults in analog circuits. In the proposed method, a fault propagation graph is first created from the circuit netlist. Standard graph theory techniques are then employed to identify a minimal set of observation points (MOP) such that, by monitoring these points, complete fault coverage can be achieved, i.e., all potential catastrophic faults of the circuit can be detected theoretically. The developed method is valuable because of the increasingly critical quality requirements for modern IC applications and the lack of existing methods that can achieve sub-ppm test escapes in the state-of-the-art. A widely used benchmark circuit, a CMOS operational amplifier, is utilized to demonstrate and validate the method. Simulation results show that all catastrophic faults can be detected by monitoring the identified MOP.

Signal spectral analysis is a dominating way of characterizing the dynamic performance of analog signals. To perform accurate spectral testing, the IEEE Standard 1241, 1658 and 1057 suggest coherent sampling. Obtaining coherent sampling, especially when signals have large distortion to noise ratios, has been a challenge for many years. With the growing need for Built-In-Self-Test (BIST) circuits for lower test cost, achieving coherent sampling is becoming more and more challenging. For signal analysis, the signals under test don't usually have sufficient purity. On-chip oscillators, such as Wien Bridge oscillators and Ring oscillator don't possess high signal purity. For high speed, low resolution DACs, the output signal purity is also low. In that case, not only fundamental bin will have spectral leakage, harmonic bins will also have spectral leakages, which makes non-coherency harder to remove.

As data acquisition systems' performance continues to increase, so does the need for a test and characterization solution to have an input test signal with purity that exceeds what is currently available in state of the art instruments. This paper presents a new method for generating ultra-pure sine wave that can be used in such applications. The pure sine wave is generated by readily available DACs with distortions that could be thousands time worse than the required system purity. Readily available ADC with similar purity as the DAC is used to measure the distortions generated by the DAC. Innovative algorithm is used to iteratively remove distortions present in the generated sine wave. Simulation results verified the proposed method by generating a -140dB ultra-pure sine wave using two DACs and an ADC with -85dB THD. A test board has been designed and measurement results demonstrated that generated sine wave has the high purity that is capable of testing an ADC with -120dB THD accurately.

Spectral testing is widely used in characterizing the dynamic performance of analog signals. Achieving accurate test results is an expensive and challenging task. This paper focuses on eliminating the challenging requirement of non-coherent sampling in the presence of an impure signal with large distortion to noise ratios. A new method was proposed that iteratively estimated noncoherent fundamental and harmonics. Comparisons are made with several widely used methods: windowing, 4 parameter sine wave fitting, and FIRE method, to address the need for this new method. They are quantitatively examined for robustness at different input signal purity and non-coherency level. The advantages & limitations of these methods are discussed. Extensive simulation results show the effectiveness and robustness of the proposed method, which can tolerate wide range of signal purity and any level of non-coherency. It can be implemented for on-chip accurate spectral test, and can also be suitable for accurate ADC spectrum test when the pure source is not available.

Accurately characterizing linearity performance of high resolution Analog-to-Digital Converters (ADCs) has been a challenging task for many years, as providing input signals whose purity is beyond ADC under test becomes harder and harder as the ADC performance becomes better. This paper proposes a novel method that uses impure test signals to accurately test linearity performance of ADC. Two nonlinear sinusoidal signals with a constant offset in between are applied to the ADC under test to obtain two output data. By identifying nonlinearities from the input and removing these stimulus errors, accurate linearity performance can be obtained. Compared with previous SEIR methods, which is vulnerable to flicker noise inherited in the input signals, the new method uses impure sinusoidal signals instead of ramp signals. Using only -40 to -70dB purity sinusoidal signals, without any Center Symmetric Interleaving (CSI) or Interleaving pattern, the proposed method is much easier to implement, and it can tolerate the influence of flicker noise, while achieving ± 0.8 least significant bit (LSB) estimation error, which is in the similar level when a pure sinusoidal is used for the same ADC linearity test. The proposed method is analyzed in detail and comparisons are made between previous SEIR methods. The effectiveness and robustness of the proposed method against flicker noise is verified through various simulations. The proposed method helps reduce the production test cost, and simplify the test setup for high resolution ADC linearity test, which is suitable for cost-effective on-chip implementation.

It is well-known that self-stabilized circuits, such as current, voltage and frequency references, are vulnerable to multiple operating points problem. This is also known as the start-up problem. In this paper, we show that the widely used analog building block, namely the op-amp, can suffer from the same problem when performance enhancement feedback is being used. In particular, slew rate enhancement circuit (SRE) can be used as an performance enhancement circuitry in the low power high speed op-amp design. For such circuit, we present a systematic method for detecting and removing Trojan state. With design example and simulation results, it is demonstrated that the proposed method can effectively remove Trojan state in the op-amp.

The Stimulus Error Identification and Removal method (SEIR) is a practical ADC Built-in self-test (BIST) solution for production test which greatly reduces the linearity requirement of the stimulus. Instead of requiring an extremely linear ramp signal in the standard histogram test, it requires two identical nonlinear ramp signals with a small, but constant offset between them. This paper presents a low cost approach to inject a high-constancy offset voltage to stimulus for BIST of SAR ADC. It utilizes a simple current source and switch on-resistance to generate the offset voltage. Compared to previous methods for offset generators, the method is robust to CDAC (capacitor DAC in SAR ADC) nonlinearity due to capacitor voltage-dependent coefficient. The proposed BIST scheme is validated through INL test of a 16-bit SAR ADC. Transistor level simulation results show that the constancy of the input offset voltage is less than 1 ppm and the estimation error on the maximum INL is less than 0.35 LSB.

Random mismatch errors in the resistor networks are one of the dominant nonlinearity sources for high resolution and high accuracy resistor DACs. It is rigorously proven and verified that ordered element matching (OEM) technology could significantly reduce the random mismatch errors. This paper proposed a novel 20-bit three-segment R-2R DAC structure based on OEM theory. It can achieve high matching accuracy by choosing and regrouping the resistors in two unary weighted resistor arrays according to their resistance measurement results. A behavioral model of proposed 20-bit R-2R DAC structure is created in MATLAB. The statistical results show a significant resistor area reduction compared with the only one existing 20bit R-2R DAC in literature.

A programmable temperature trigger circuit with thermal hysteresis that is suitable for on-chip thermal management applications is proposed. The circuit utilizes a simple Schmitt Trigger structure. Both the location and the width of the hysteresis window are programmable. The temperature trigger circuit is designed in a 0.13um IBM CMOS process and operates with a supply voltage of 1.2V. Both the power dissipation and the silicon area are very small.

A temperature to digital converter (TDC) that does not require either a reference generator or an ADC and that exhibits low supply sensitivity, small die area, and low power consumption is introduced. A prototype circuit designed to support power management applications over the [60 °C, 90 °C] temperature range was implemented in an IBM 0.13μm CMOS process with a 1.2V power supply for use as either a temperature trigger or a digital thermometer. Simulation results show the maximum temperature error over this range is less than ±0.5°C. The total silicon area for the TDC is only .004mm2.

Frequency drift is an important issue and is difficult to be avoided in ADC testing. The power leakage caused by frequency drift in the ADC output spectrum cannot be removed by conventional methods. This paper proposes a new algorithm which can estimate the ADC specifications accurately when there is frequency drift. The output of the ADC is collected as Ks segments. Phase correction is applied to those segments to make the initial phase of each segment is zero. And those segments are averaged after phase correction to remove the frequency drift effect. Simulation results show that this algorithm can obtain the ADC specifications correctly when the input frequency drifts under 100ppm/second.

Clock jitter is a crucial factor in high speed and high performance Analog-to-Digital Converter (ADC) testing. Random clock jitter increases the noise floor in the ADC output spectrum making it difficult to obtain the true ADC Signal to Noise Ratio (SNR). Periodic Jitter generates spurs in the ADC output spectrum. Another well-known challenge is to achieve precise coherent sampling. This paper proposes an efficient and accurate ADC spectral testing method that completely eliminates the need for coherent sampling and very effectively separate clock jitter from ADC noise, thus allowing the true ADC spectral parameters to be accurately tested with an imprecise sampling clock. Simulation results of ADCs with different resolutions demonstrate the functionality and accuracy of the method.

A solution of thermal noise thermometer in integrated circuit (IC) is presented in this paper. By limiting the dynamic range and bringing in IC solution, bottlenecks of high resolution and high speed requirements are broken. In this design, a multi-stage pre-amplifier is added to magnify the noise and predictions of output noise power from different sources are given after mathematical analysis. Consequently, the design conditions of the amplifier for maintaining the thermometers accuracy are generated. A 6-bit resolution analog-to-digital converter will be used to sample the signal and statistical theories are explored to develop methods which help acquire power and temperature information from the sampled codes. The design concepts are eventually verified by simulations. After one-point calibration at 27°C, the integral non-linearity of this method is 0.59°C over a temperature range from −40°C to 105°C.

A cascode and transconductance with capacitances feedback compensation (CTCFC) for multistage amplifiers is proposed in this paper. By adding a transconductance with capacitor feedback across the output stage, the shorting effect of this capacitor is eliminated, which enlarges the gain at higher frequency region. This capacitor can also help stabilize no load configuration. The other compensation capacitor through cascode from the output to the first stage simplifies the circuit and provides zeros to further increase the bandwidth. The proposed technique has been verified by an implementation in a 0.6μm CMOS process. The gain-bandwidth product (GBW) is 3.6MHz under a capacitive load of 1nF. The slew rate is 2.6V/μs and the current consumption is 88μA which shows an improvement in IFOMLperformance.

A calibration technique for SAR analog-to-digital converters is proposed in this paper which is ready to be integrated on chip. This technique is based on the integral nonlinearity (INL) test and utilizes one redundant bit and extra two quantization bits to improve the calibration accuracy. In the calibration mode, mismatch errors are saved as higher-bit level INL information and then translated to calibration codes. During the conversion, higher-bit level outputs are adjusted and truncated to generate the required bits. Finally, 0.375LSB improvement of INL is observed by theoretical analysis and the effectiveness of this method is verified by simulations in which the maximum INL is reduced from 0.9LSB to 0.23LSB.

Linearity test of an analog-to-digital converter (ADC) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. For high performance ADCs, the overall manufacturing cost could be dominated by the long test time and the high-precision test instruments. This paper introduces the ultrafast stimulus error removal and segmented model identification of linearity errors (USER-SMILE) method for high resolution ADC linearity test, allowing the stimulus signal's linearity requirement to be significantly relaxed and the test time to be reduced by orders of magnitude compared to the state-of-art histogram method. The USER-SMILE algorithm uses two nonlinear but functionally related input signals as ADC excitations and uses a stimulus error removal technique to recover test accuracy. The USER-SMILE algorithm also uses the ultrafast segmented model identification of linearity errors (uSMILE) approach to dramatically reduce test time while achieving test accuracy and coverage superior to the histogram method. The USER-SMILE algorithm is validated by extensive simulation with different types of ADCs, different resolution levels, and different types of input signals including nonlinear ramps, nonlinear sine waves and even random input signals. Statistical simulation results show that for a 16-bit SAR ADC, with two 1 hit/code nonlinear ramp signals, the INL test error is within +/- 0.4LSB.

Clock jitter is a crucial factor in high speed and high performance application. Traditional jitter measurement method relies on precise and expensive instrumentations. This paper proposes a low cost jitter measurement and separation method. Instead of using traditional time internal analysis equipment, a simple Analog-to-Digital Converter (ADC) is used as the jitter measurement device. The clock under test is applied as the sampling clock of an ADC while the ADC is sampling a full scale sine wave. The ADC output contains the information of the clock jitter. The algorithm will separately detect the effects of Periodic Jitter, Dual-Dirac Jitter and Random Jitter, and accurately compute the rms value of each jitter component. This method offers great potential for wide use in low cost applications and especially in on-chip or on-board jitter measurement applications. Simulation results demonstrate the functionality, accuracy and robustness of the proposed low-cost jitter measurement method.

Identifying and removing the undesired stable operating point (also called “Trojan state” in analog circuit) is one of the most important problems in circuit design. In this paper, an innovative divide and contraction verification method against Trojan states is proposed. Unlike the traditional methods to find all operating points, it only targets searching the voltage interval containing undesired stable operating point. Based on this, a monotonic divide and contraction algorithm (MDC) is proposed, it could verify the existence of Trojan state in high efficiency. Simulation results show that this method is effective and efficient in identifying Trojan states and verifying the efficacy of Trojan state Elimination (TSE) circuits which is commonly termed start-up circuits.

A systematic method is proposed for automatically identifying and breaking positive feedback loops (PFLs) in Trojan States Vulnerable Circuit. The method first converts the netlist of a circuit into a directed dependency graph (DDG) and then partitions the DDG into strongly connected components (SCCs). It then employs graph theory techniques to detect all PFLs and locate the break-points for every SCC. The proposed method could identify the circuit's vulnerability to Trojan States only by its structure without the computation of DC solutions and it also provides insights on how and where to break the PFLs such that break-loop continuation methods can be applied. With Sub-Bandgap reference and widlar-Banba examples, it is demonstrated that the proposed approach can effectively identify all the PFLs and break-points.

Production test is a significant contributor to the manufacturing cost for high performance analog and mixed-signal products. Linearity test and spectral test are two main categories in ADC testing, and linearity test cost is usually the largest component in the test cost. For spectral testing, it is a very challenging task to precisely control the amplitude and frequency of input sinusoidal signal. Over-range amplitude results in clipping ADC output and non-coherent sampling results in spectral leakage. To reduce ADC test cost dramatically, a new algorithm is proposed in this paper. The new algorithm can simultaneously perform linearity test and spectral test with only one-time data acquisition. Targeted for realizing co-test of linearity and spectral performance under non-coherent sampling and amplitude clipping, a new accurate method for identifying the non-coherent and clipped fundamental is introduced. The residue after removing the identified fundamental from raw data is used to obtain the linearity and spectral characterizations. Simulation results and measurement results against the standard test methods collaborate to validate the accuracy and robustness of the new solution.

A systematic method is proposed for automatically identifying positive feedback loops (PFLs) in analog/mixed-signal circuits. The method first converts the netlist of a circuit into a directed dependency graph (DDG) which captures the critical relationships among branch currents and node voltages. It then utilizes graph theory techniques to find all feedback loops from the DDG and finally, criterion are developed to determine the PFLs. Since multiple states is caused by the PFLs, this method could identify the circuit's vulnerability to undesigned operating points only by its structure without the computation of DC solutions. The proposed approach is implemented in program and simulation results show it could identify all the PFLs very robustly.

Jitter is a crucial factor in high speed and high performance ADC testing. This paper proposes an efficient and accurate jitter estimation method based on one frequency measurement. Applying simple mathematical processing to the ADC output in time domain, the RMS of jitter and noise power are obtained. Furthermore, prior information of harmonics does not need to know before the processing. The algorithm is robust enough that non-harmonic spurs does not affect the estimation result. Using the proposed algorithm, specifications of SNR and ENOB of the ADC under test can be obtained without jitter effect. Simulation results of ADCs with different resolutions show the functionality and accuracy of the method.

Random mismatch errors in the resistor networks are one of the dominant nonlinearity sources for high resolution and high accuracy resistor DACs. This paper applies the theory of ordered element matching in a high resolution segmented R-2R DAC. It can achieve high matching accuracy by regrouping the resistors in the MSB array according to their resistance ranks obtained by the INL test. The implementation only requires adding some additional digital circuits to the typical design. A behavioral model of 18-bit segmented R-2R DAC is created in MATLAB. The statistical results show a significant resistor area reduction compared with state of the art.

An empirical reliability model for electromigration-induced failure in metal interconnects under thermal, electrical, and thermal gradient stress is introduced. Based upon the limited reported measurements on static thermal gradient stress that are available, this model incorporates thermal gradient stress into the probability density function of the time to failure, tF. With this model, temperature measurement accuracy and temperature gradient measurement accuracy requirements for multi-site on-chip sensors that can be used in power/thermal management algorithms are developed that target achieving 10% accuracy in the median time to failure (MTF) of a circuit.

Spectral testing is important to measure the frequency characteristics of an Analog to Digital Converter. It is an expensive and challenging task to perform coherent sampling and to acquire highly pure signal generators for spectral testing. For the first time, a method that can eliminate the requirements of both coherent sampling and highly pure signal generators to perform accurate spectral test is proposed. Simulation results show the ability of the proposed method to accurately test a 15-bit ADC using a non-coherently sampled input signal with SFDR of 39dB. Furthermore, the robustness of the proposed method over the whole range of non-coherency is presented. The method can be applicable for ADC production test.

Several methods that can be used to verify effectiveness of startup circuits in eliminating known stable Trojan operating states will be discussed. It will be shown that some widely used approaches do not guarantee Trojan states have been removed. Some of the methods introduced appear to be more practical to work with than others. These methods can also be used to identify the presence of unknown stable Trojan states in many useful circuits.

An accurate, small, low-power CMOS temperature sensor for on-chip thermal monitoring is proposed. The temperature sensor utilizes the temperature characteristics of the threshold voltage of a MOS transistor to sense temperature and is quite linear over the in temperature range (-20C, 100°C). The threshold-based temperature sensors were designed in the ON Semiconductor 1P6M (Single Poly, 6 Metal) 180nm process with a 1.8V supply voltage. The die area of this circuit is only 14.8μm×22.2μm. It has low power consumption of about 1.026μW at a 1% duty cycle. Measurement results show that a batch of 5 temperature sensors have a nonlinear error bounded of -0.21°C to +0.17°C with a one-point calibration and batch slope/curvature correction over the target operating temperature range (-20°C, 100°C).

Test time controls the competitiveness and viability of new precision products in two fundamental ways: it determines final test cost which is a major part of the recurring manufacturing cost, and it determines characterization test time which directly adds to time to market. This paper introduces a new test strategy aimed at dramatically reducing test time for precision analog and mixed signal products. The strategy is termed SATOM for Simultaneous AC-DC Test with Orthogonal Multi-excitations. In SATOM, a device under test is excited with multiple mutually-orthogonal stimulus signals that are simultaneously applied at different input points of the device. A single set of response data is acquired and an intelligent processing algorithm is used to simultaneously compute multiple AC and DC test specifications for the device. This results in a reduction of well over 90% in test time for those specs, with no negative impact on test coverage and test accuracy. Extensive measurement results demonstrated effectiveness, efficiency and robustness of the new method.

For spectral testing of Built-in Self-Test Analog to Digital Converters, it is a very challenging task to precisely control the amplitude and frequency of input sinusoid signal. Amplitude over-range results in clipping ADC output and non-coherent sampling results in spectral leakage. In this paper, a new method is proposed that provides accurate spectral results even when the input to ADC is both over-ranged and non-coherently sampled. This relaxes the condition to have precise control over the input signal and thus decreases the cost. The method includes fundamental identification, removal and residue interpolation to obtain accurate spectral results. Simulations show the functionality and robustness of proposed method with both non-coherency and amplitude over-range. Measurement results of a commercially available 16-bit SAR ADC are used to verify the method for both functionality and robustness.

As the Systems-on-Chips (SoCs) complexity increases, test cost contributes more in the total cost. Especially, test of deeply embedded analog and mixed signal blocks are the most costly test. Built-In Self-Test (BIST) is considered as a low cost substitution of traditional production test. This paper presents a low cost method for testing ADC's offset and gain error. This is a complement of previous published linearity and spectral performance test methods. The simulation results show the method has good accuracy.

A novel technique to generate spectrally pure sinusoidal signals is proposed. The technique provides a dramatic improvement in spectral performance compared to the existing state of the art. With the proposed approach, spectral performance is inherently robust to variation in operating frequency and spectral characterization is programmable over frequencies. A circuit using extremely low cost operational amplifiers and 5 % accurate passive components has been built that can generate a sine wave with THD of lesser than -100dB at frequency, f=2.737 KHz .

A simple low-power current reference using dual-threshold MOS transistors is introduced. The area required for this reference is small and the sensitivity of the output current to the supply voltage is low. Simulation results show that an implementation of this current reference in a TSMC 0.18um CMOS process with a 1.8V power supply is constant to within ±1.25% over the temperature range of -10°C to 100°C. In this implementation, the active area is 86 μm2, the power dissipation is 72μW, and the worst process corner nonlinearity due to temperature variations is bounded by ±4.16%.

For high performance analog and mixed-signal products, production test is a significant contributor to the recurring manufacturing cost. For high resolution ADCs, the cost of build can be dominated by test cost, of which linearity test cost is often the largest component. This paper introduces a new algorithm that dramatically reduces ADC linearity test cost. The algorithm takes a system identification approach using a segmented non-parametric model that captures both linear errors (mismatches, etc.) and truly nonlinear errors (voltage coefficients, etc.). By avoiding the gross inefficiencies inherent in conventional linearity test solutions, the new algorithm is able to reduce the required test data by a factor of over 100. The algorithm works for various types of ADCs, including SARs and pipelines. Simulation results and measurements against the gold standard servo-loop test validate the accuracy of the new solution. Results from multiple case studies involving both good and poor ADCs demonstrate that the new method achieved several times better precision than standard histogram test, while using two orders of magnitude less test data and hence test time.

Linearity and spectral performance test contributes most cost of ADC test. This paper presents a new method for testing an ADC's SNR from its linearity test data. The method does not require additional data acquisition or accurate sinusoidal stimulus. Data collected for linearity test is used to compute the input noise power and test ADC's SNR. Both simulation and experimental results show that the proposed method can estimate SNR value accurately.

A new on-die temperature sensor that operates at low supply voltages and exhibits low process sensitivity and good linearity over a wide temperature range is introduced. When compared to conventional structures which have limited supply voltage headroom at the slow-n process corner, the new structures have sufficient headroom to practically operate well over all process corners. When implemented in a TSMC 0.1 Sum process with a nominal supply voltage of 1.8V, simulation results show the maximum temperature linearity error is reduced from 1.5°C to less than 0.3°C at the NMOS slow process corner and with negative 10% Vdd variation.

Spectral testing is one of the frequently encountered problems in signal processing and communications. It is a challenging task to obtain coherent sampling for accurate spectral testing. Windowing techniques are widely used to perform spectral testing when the sampling is slightly noncoherent. This paper proposes a new Fundamental Identification and Replacement (FIR) method. The proposed method can estimate the spectral characteristics accurately without requiring coherent sampling. The method is robust to any level of non-coherency, which makes on-chip spectral testing possible. The new method is computationally efficient and is applicable for high resolution spectral testing. Furthermore, the proposed method can perform both single tone signal test and multiple tone signal test accurately. The method gives accurate results even in situations when the windowing techniques cannot give correct results. Simulation results show the robustness and the computational efficiency of the proposed method. The method is also validated with the experimental data.

Coherent sampling is required in ADC testing. Unlike production testing in which fractional frequency is available, only sampling clock of ADC is available for ADC Built-in Self-test (BIST). Triangular stimulus generator controlled by sampling clock of ADC cannot provide enough information because same voltages are sampled in every period. To carry out valid data acquisition, different voltages in different period should be sampled. Instead of generating fractional frequency, a method of introducing delay to every ramp in triangular wave is proposed in this paper. An 8-bit digital to time converter (DTC) is designed to provide needed number of delays. A control scheme is proposed to provide both phase control of triangular stimulus and testing control of BIST. Simulation results show control scheme works well for linearity test and delayed triangular wave provides valid data acquisition for histogram test. Errors in delay affect test results very little.

Data acquisition time and accurate instrumentation are the most significant contributors to ADC test cost. For most ADC products, static linearity (INL/DNL) test is required. This paper presents a methodology for estimating an ADC's dynamic performance from its tested INL data, without requiring additional data acquisition or additional accurate sinusoidal sources. The tested INL(k) data is used to compute the power at harmonic frequencies and estimate ADC's dynamic specifications such as THD and SFDR. Memory and computation requirement is very small comparing to that in traditional spectral testing. When combined with a BIST approach for INL testing, this method offers a very low cost BIST solution to ADC dynamic performance testing. Both simulation and experimental results show that the proposed method can estimate THD and SFDR values accurately.

Due to the positive feedback and the time varying clock signal, the operating point of each transistor in dynamic comparators is time varying and cannot be analyzed using traditional Op-Amp-based small signal analysis. Until recently, a balanced method is proposed to effectively get the analytical models for random offset caused by variations in process parameters. Meanwhile, it has been shown that mismatches from parasitic capacitors are also significant contributors to overall offset. However, the energy storage and nonlinear feature of capacitor make it even more challenging to analytically predict the capacitive mismatch induced offset. In this work, the previous proposed balance method is generalized and applied to tackle the problem of capacitive mismatch induced offset. The analytical models are derived to explicitly show offsets caused by capacitor mismatch at different internal nodes. The insights are obtained on identifying the sensitive nodes to capacitor mismatch and on how to reduce the offset. The numerical example validates the effectiveness of the analytical models.

Traditional linearity testing of ADCs involves using a spectrally pure or a highly linear stimulus, along with a large number of samples per code to average out the effects of noise. Test equipments need to house expensive instruments to provide the highly linear stimulus. The large number of samples required for the procedure results in long test times. These two factors are prime contributors to the test cost. In this paper, algorithms which use low linearity stimuli and a Kalman Filter to reduce both the hardware resources and the test time for the test procedure have been proposed. Simulations results for a 14-bit ADC show that a 7-bit linear stimulus with one sample per code can be used to measure the INL of the ADC with a maximum estimation error of 1 LSB.

Attaining high matching property of the current sources is very important for the design of high-speed high-accuracy current-steering DACs. This paper presents a novel calibration technique-complete-folding, which achieves the high matching accuracy by selectively regrouping current sources into a fully binary-weighted array based on the current comparisons after chip fabrication. The implementation only requires an analog current comparator and some digital circuitry. The minimum requirement of analog circuits makes the complete-folding calibration suitable for the DAC design in the low-voltage process. Statistical results with a behavioral model of a 14-bit segmented DAC in MATLAB show that complete-folding calibration can reduce the total gate area of current sources by a factor of almost 1200 compared to that using intrinsic-accuracy method. Additional results also show that the new calibration technique has the superior performance in compensating random mismatch errors compared with state-of-the-art.

Code and voltage dependence of the finite output impedance is a major contributor to current-steering DACs' nonlinearity. This paper introduces a novel output impedance linearization technique that very effectively reduces this code and voltage dependence. The linearization is achieved by using a small linearization DAC switched with control signals opposite to those for the main DAC. The area and power overhead is less than 5% of the main DAC. Simulation results with a 14-bit segmented current-steering DAC in standard 0.18μm CMOS process show that the DAC's integral nonlinearity due to finite output impedance is improved by almost 5 bits. Additional results also show that the linearization technique is very robust to random mismatch errors.

Linearity test and spectral test are two main contributors of ADC test cost which includes data acquisition time and accurate instrumentation. This paper presents a new method for estimating an ADC's spectral performance from its tested INL data. The method does not require additional dedicated test circuitry or data acquisition. The results from INL test are used to compute harmonic distortions and other spectral specifications of the ADC. Memory and computation requirements are very small comparing to those in traditional spectral testing. When combined with a BIST approach for INL testing, the proposed method offers a very low cost BIST solution to ADC spectral testing. Both simulation and experimental results show that the proposed method can estimate THD and SFDR values accurately.

ADC in SOC usually has no connection to the outside. Built-in self-test is a good way to verify this block's performance. Stringent requirement of stimulus generator is the most important limitation of ADC BIST. Several methods of using stimulus with low linearity to test ADC with high linearity have been reported for standalone production test. These methods can be adapted for ADC BIST to reduce the BIST cost overhead. This paper investigates signal patterns that can be used in low cost BIST scheme. Two cost effective stimulus generator structures are presented. Simulation results shows that the generated signal with less than 7 bits linearity can be used to test a 16 bits ADC. The estimation errors of INL are less than 0.65 LSB.

The relationship between yield, area, and impedance distribution in dual-string DACs is developed. Optimal area allocation and impedance distributions strategies for maximizing yield in the presence of local random process variations are introduced. Simulation results show that a factor of 4 or more reduction in area for a given yield is possible if typical area/impedance allocations are replaced with an optimal area/impedance allocation.

In a dynamic comparator, it's always challenging to analytically predict the input offset voltage due to the existence of the internal positive feedback and transient process. In this paper, a simple method is presented to accurately estimate input offset voltages caused by process variations in dynamic comparators. The "Lewis-Gray" comparator implemented in TSMC0.25mum process is applied as an example to verify the effectiveness of the analytical method. Based on the SPICE level 1 model, the method shows good agreements with Monte Carlo transient simulation based on the sophisticated BSEVI3V3 model. The analytical results allow the circuit designers to fully explore the tradeoffs in comparator design, such as offset voltage, area and speed. To illustrate the potential, the analytical method was used to re-size the "Lewis-Gray" structure to reduce its random offset while maintaining a constant total area. After the optimization, input offset voltage has been reduced by 41% compared with its original sizing.

Adjustable hysteresis CMOS Schmitt trigger design strategies are investigated and two new inverter based designs are proposed. The sizing of the two feedback inverters controls the two trip points of the structure independently. By the addition of voltage controlled current sinking and/or sourcing transistors, the hysteresis window can be easily moved without changing its width. Moreover the new designs are immune to the kick-back noise coming from the succeeding blocks.

This work presents a system identification-based reduced-code testing method for pipeline ADC’s linearity test. In the method, the pipeline ADC under test is identified by characterizing the two most critical parameters in each stage, the stage gain and the comparator offset. The transfer function is investigated to obtain the effects of the gain error and comparator offset on ADC’s linearity performance. With the measurements of a small set of specific transition levels or code bin widths, the system parameters of interest can be achieved using only straightforward linear calculations. The identified model is then used to compute the ADC’s full-code linearity performance. Comparing to standard histogram-based full-code linearity test methods, the proposed method can reduce the data capture time by a factor of several hundreds without appreciably degrading the testing accuracy. Both simulation results and experimental results are included to demonstrate the efficacy of the proposed method.

A rigorous and complete analysis of the deterministic DEM (DDEM) DAC performance is presented. With this analysis, DDEM DAC's equivalent linearity as ADC static linearity test stimulus source can be precisely predicted. Simulation result is given to validate this theoretical analysis.

Digital testing is much easier and cheaper than analog and mixed-signal testing because of the straightforward connections and the low-cost testers. This paper presents a fully digital-compatible built-in self-test strategy for ADC linearity testing using all digital testing environments. Onchip, low-accuracy DACs, which are area efficient and simple to design, are implemented as the stimulus generator. ADCs’ nonlinearities are tested using a histogram-based method under the control of a logic block. The described strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INLkerror of 12-bit ADCs to ±0.2LSB accuracy level using only 7-bit linear DACs.

High-precision ADC testing is a challenging problem because of its stringent requirement on test signal's linearity. This work introduces a method using a nonlinear stimulus signal for testing linearity of high-resolution cyclic and pipelined ADCs by exploiting their architecture information. Simulation and experiments show that 16-bit ADCs can be tested to 1-LSB accuracy by using a 7-bit linear signal. This approach provides a solution to both the production and on-chip testing problems of high-resolution ADCs.

Conspicuously absent in the literature are explicit relationships between the output voltage and temperature of bandgap references. In this paper an explicit relationship for the output voltage of a popular bandgap reference structure is developed. Within the context of this explicit relationship, temperature stability properties of references are explored

This work introduces a multi-segment bandgap reference circuit with self-calibration. Thermal characteristics of the bandgap circuit were modeled using test results under normal temperatures. With the characterization information, appropriate circuit parameters were calculated for different temperature intervals and used to adjust the inflection point of the bandgap curve as the temperature changes, in order for the reference circuit to achieve high thermal stability. Simulation results show that the proposed circuit can achieve a better than 0.5 ppm//spl deg/C temperature coefficient over a range of 140/spl deg/C. This circuit is compatible with most of the existing bandgap circuit structures and can be used in low-voltage designs.

This work proposed a built-in self-test (BIST) strategy for DAC linearity test by utilizing the deterministic dynamic element matching (DDEM) technique in a common flash ADC. DDEM technique allows low-resolution and low-accuracy ADCs work as test devices. In order to provide high resolution/accuracy test abilities, a fine quantization stage and an input dithering DAC are incorporated. In this paper, the architecture of the test system and the test procedure are described. The test performance is analyzed theoretically and verified by numerical simulation. Simulation results show that a two-step flash ADC composed of a 6-bit coarse DDEM stage and a 6-bit fine stage, plus an incorporated 5-bit dithering DAC, with linearity of all the blocks no more than 6 bits, is capable of testing 14-bit DACs.

In this paper, the well-known equation, which explicitly shows the temperature behavior of the I/sub C/-V/sub BE/ characteristics of the transistor, is applied to analyze a specific bandgap reference circuit. The theoretical analysis clearly characterizes some important features of the circuit, such as the value of the bandgap output, the relationship of the inflection point and the circuit parameters, the curvature of the bandgap curve and so on. Spectre simulations show a good consistency of the analysis. Based on the analysis, a new approach for designing high-precision references is also proposed.

This work introduces an efficient code-density linearity testing algorithm for ADCs that can achieve high accuracy within short test time. The proposed algorithm uses Kalman filtering to suppress the effect of errors in the histogram counts based on characteristics of input noise and circuit mismatches. Appropriate versions of the algorithm for ADCs of flash and pipelined architectures are introduced respectively. Simulation results show that this approach can reduce the INLkestimation error by over 50% and achieve desired accuracy with a much smaller number of samples as compared to the conventional algorithm. Simulation and experimental results show that the proposed algorithm can significantly shorten the linearity test time by a factor of 10 or higher. Therefore, it can enable test and help maintain the quality of high-performance ADCs, and reduce the production test time and cost for medium and low resolution ADCs

The bottleneck of DAC testing is the fast and accurate measurement devices. Production testing of high-resolution DACs with gigahertz clock rates is a challenging problem, and there is no widely adopted approach for on-chip testing of precision DACs in an SoC system. This work presents a new approach for testing high-resolution DACs. High speed data acquisition is achieved with flash ADCs; sufficient resolution is provided by dithering; and high test accuracy is guaranteed by the proposed data processing algorithm. This method provides a potential solution to both the production and on-chip DAC testing problems. Simulation results show that the static linearity of 14 bit DACs can be tested to better than 1 LSB accuracy, and dynamic performance of more than 85 dB SFDR can be tested with 1 dB accuracy, using 6-bit ADCs and dithering. Experimental results included in the paper also affirm the performance of the algorithm in testing high-resolution DACs using 6-bit ADCs

This work describes a linearity test strategy for ADCs that uses stimuli with precision much lower than the ADC resolution and tolerates environment nonstationarity. This approach can be applied to testing ADCs of very high performance, such as 16-bit or higher resolutions and more than 1 MSPS sampling rates, to which there is hardly a well-established solution for full-code test. Simulation and experimental results show that a 16-bit ADC can be tested to 1-LSB accuracy by using input signals of 7-bit linearity in an environment with more than 100 ppm per minute nonstationarity. The proposed method can also help control the cost of ADC production test, extend the test coverage and enable built-in self-test and test-based self-calibration.

A novel, on-chip transfer function calibration scheme is introduced to the classical resistor string DAC architecture. A 16-bit, quad channel, resistor string DAC with exceptional accuracy is fabricated on an ultra-low-cost, 0.5/spl mu/m, 5V CMOS process. Monotonicity is achieved by voltage interpolation and absolute accuracy errors are improved by 100/spl times/ using full transfer function calibration at final test. An on-chip arithmetic logic unit (ALU) linearly interpolates calibration coefficients saving memory, and a high-effective-resolution cal-DAC preserves differential linearity (DNL) performance while correcting integral linearity errors. Separate cal-DACs correct for offset and gain errors. Each DAC channel occupies 4mm/sup 2/ die area, consumes 750/spl mu/A, and settles in 10/spl mu/s, while offering up to +/- 500/spl mu/V absolute accuracy across its transfer curve. The chip has built-in DFT and uses one time programmable memory with read-back. The device can be calibrated and tested with a single insertion at final test. This paper discusses the architecture, testing, calibration and optimization details.

This work presents a deterministic dynamic element matching (DDEM) approach which is applied to low precision DACs to generate stimulus signals for ADC testing. Both simulation results and experimental results from a fabricated DDEM DAC are presented to verify the performance. The ADC testing performance of an 8-bit DDEM DAC (linearity less than 5 bits without DDEM) is comparable to or better than the best results reported in the literature using on-chip linear ramp generators. The DDEM technique offers great potential for use in both production test and built-in-self-test(BIST) environments.

The fast Fourier transform is the ubiquitous method of choice for spectral testing. However, its correct application to periodic signals requires either strict coherent sampling, or careful windowing, or other techniques that are computationally inefficient. This work introduces a new method for achieving accurate spectral testing for periodic signals without the need for coherent sampling or windowing. Furthermore the method is computationally very efficient with only minimal addition to the computational complexity of FFT. The method is validated with both simulation data and experimental data. Extensive controlled simulation indicates that the method is very robust to errors in signal frequency, phase, amplitude, additive noise, and so on. Statistical analysis and comparative studies demonstrate that the proposed method achieves spectral testing accuracies similar to those obtained with perfect coherent sampling in an ideal noise-free environment.

As the performance of Analog-to-Digital Converters continues to improve, it is becoming more challenging and costly to develop sufficiently fast and low-drift signal generators that are adequately more linear than the ADC for the purpose of linearity testing. This work relaxes the linearity requirements on the signal generators used for ADC testing by alternatively employing multiple non-linear inputs. Assuming minimal prior knowledge of the input non-linearity, a testing methodology is introduced that is based upon first identifying and computationally removing the source non-linearity and then accurately estimating the ADC linearity. Production test hardware is used for validating the performance of this testing methodology using a high performance 16-bit SAR ADC as a test vehicle. Integral linearity error readings are identified to well within the +/-2 LSB range of the device specification by using only 8-bit linear inputs. This approach provides an enabling technology for costeffective full-code testing of high performance ADCs in production test and for a cost-effective implementation of built-in self-test (BIST).

A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogram-based algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n -bit ADC by using a ramp signal of much less than n -bit linearity and a shifted version of the same nonlinear ramp as excitation. The performance of the algorithm is comparable to that of the traditional method which uses ( n + 3)-bits or a decade more linear input signals. Complete algorithm description, extensive simulation results and experimental results obtained from using a production tester on commercially available ICs are presented to validate the potential of this algorithm.

A novel adaptive learning algorithm is presented for the repetitive tracking control of a class of unstable nonminimum phase systems. After each repetitive trial, a least squares method is used to estimate the system parameters. The output tracking error and the identified system model are used through stable inversion to find the feed forward input, together with the desired state trajectories for the next trial. An adaptive backstepping based tracking controller is used in each trial to ensure the regulation of the desired state trajectories. Simulation results demonstrate that the proposed learning control scheme is very effective in reproducing the desired trajectories.

This paper is concerned with optimal motion planning of a flexible space robot. The robot is assumed to consist of two flexible links which are attached to a rigid space station floating in space. The optimal motion planning is first formulated as a two-stage functional optimization problem, which is further simplified into an optimal trajectory planning problem using recently developed stable inversion theory. The motion planning is optimal in the sense that the system performance measured by the manoeuvring time together with control and structural vibration energy is minimized. Besides, the controller also keeps the interference from the arm to the space station satisfactorily small. A suboptimal solution to the corresponding trajectory planning problem is obtained via two decoupling on the linearized zero dynamics. One is of the hyperbolic and the nonhyperbolic parts, and another is of the stable and unstable parts. Numerical examples are given to demonstrate the effectiveness of this approach.

Underactuated mechanisms will provide low-cost automation, easily overcome actuator failures, and be particularly useful for space applications because of their reduced mass and lower power consumption. In space underactuation can be effectively introduced in robot manipulators. Such mechanisms will however be difficult to control because of the fewer number of actuators in the system. It is shown that when the actuated joints do not have brakes, it is possible to bring the system to a complete rest and converge the actuated joints to their desired values, provided the system maintains zero momentum and none of the unactuated joints are cyclic coordinates. To converge both the actuated and the unactuated joints to their desired set of values, it is assumed that the number of actuated joints is more than the number of unactuated joints, and the unactuated joints have brakes. It is shown that if there exists sufficient dynamical coupling between the set of actuated and unactuated joints it is possible to converge all the manipulator joints to their desired values.>