EDBT 2026 Demo / reviewers in the wild / expert
Saurabh Kumar Raina
dblp:08/4368
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › computer arithmetic
floating-point arithmetic |
0.0 | 1 | 2004 | Accelerating Correctly Rounded Floating-Point Division when the Divisor Is Known in Advance · IEEE Trans. Computers 2004 |
Processor architecture and microarchitecture › computer arithmetic › floating-point arithmetic
fused multiply-add |
0.0 | 1 | 2004 | Accelerating Correctly Rounded Floating-Point Division when the Divisor Is Known in Advance · IEEE Trans. Computers 2004 |
Processor architecture and microarchitecture
instruction set architecture |
0.0 | 1 | 2004 | Accelerating Correctly Rounded Floating-Point Division when the Divisor Is Known in Advance · IEEE Trans. Computers 2004 |
Methods — techniques the papers use, named apart from their topics
fused-mac · 0.0double-word approximation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2004 | Accelerating Correctly Rounded Floating-Point Division when the Divisor Is Known in AdvanceabstractWe present techniques for accelerating the floating-point computation of x/y when y is known before x. The proposed algorithms are oriented toward architectures with available fused-mac operations. The goal is to get exactly the same result as with usual division with rounding to nearest. It is known that the advanced computation of 1/y allows performing correctly rounded division in one multiplication plus two fused-macs. We show algorithms that reduce this latency to one multiplication and one fused-mac. This is achieved if a precision of at least n+1 bits is available, where n is the number of mantissa bits in the target format, or if y satisfies some properties that can be easily checked at compile-time. This requires a double-word approximation of 1/y (we also show how to get it). Compilers to accelerate some numerical programs without loss of accuracy can use these techniques. Nicolas Brisebarre, Jean-Michel Muller, Saurabh Kumar Raina |
IEEE Trans. Computers | 3 |