This paper discusses the results of several design-for-testability techniques implemented in a multichip module (MCM). MCM test issues discussed include boundary scan, Built-In-Self-Test (BIST), concurrent test sequencing, and module level test. Analyzing the results of the DFT attributes is necessary to determine effectiveness of the overall test strategy, improve upon various techniques, and learn lessons that may be carried into subsequent generations of MCM design. A discussion of the analysis and the lessons learned is presented, as well as a brief discussion on future planned implementations.>

This paper highlights the development of a multichip module (MCM) design-for-testability methodology for an application intended for use in a fully electronic active matrix LCD flight instrument. MCM test issues discussed include design-for-testability, substrate test, known-good die (KGD), and module level test. The design incorporates IEEE 1149.1 and built-in-self-test features. Bare die pretest is accomplished with a ball grid array (BGA) chip carrier approach. The hardware consists of a mature digital design comprised of application specific and industry standard integrated circuits. Challenges and lessons learned are addressed along with next generation test approaches.>

Multichip module technology has been shown to offer significant improvements for electronics equipment in the areas of miniaturized size, reduced weight, capability for higher frequency operation, improved thermal performance, and improved reliability. Production applications for multichip modules (MCMs) have grown from high-end computer and aerospace modules to include such diverse products as telecommunications, automotive, and consumer electronics modules. One of the keys to economic success in all applications is the achievement of high manufacturing yields. Yield losses must be kept very low compared with module costs in order to remain economically competitive. Two parameters with a very strong impact on manufacturing yield, known-good components entering assembly and test strategies at various levels of assembly, are discussed. Current industry practice is surveyed and recent progress on MCM infrastructure development is summarized.>