By 2030, we will design monolithic chips with hundreds of billions of transistors and 3D-integrated systems surpassing a trillion—pushing the boundaries of complexity and creativity. These designs will emerge from millions of lines of RTL, but will they be crafted by engineers, or by intelligent agents? Generative AI is no longer a curiosity; it is reshaping the EDA landscape. Are we witnessing the birth of an era where autonomous AI agents orchestrate entire design flows, transforming high-level intent into 2nm, DRC-clean, timing-optimized layouts—bypassing traditional toolchains? Or will quantum computing claim the crown, solving optimization problems once deemed intractable? Or will most of this still be a decade out? This keynote looks beyond incremental progress to a future where heterogeneous compute—CPUs, AI accelerators, and quantum processors—collaborate seamlessly. What breakthroughs are needed and what disruptions and paradigm shifts lie ahead as we try to reimagine the very nature of chip design?

Recent breakthroughs in Large Language Models (LLMs) and Large Circuit Models (LCMs) have sparked excitement across the electronic design automation (EDA) community, promising a revolution in circuit design and optimization. Yet, this excitement is met with significant skepticism: Are these AI models a genuine revolution in circuit design, or a temporary wave of inflated expectations? This paper serves as a foundational text for the corresponding ICCAD 2025 panel, bringing together perspectives from leading experts in academia and industry. It critically examines the practical capabilities, fundamental limitations, and future prospects of large AI models in hardware design. The paper synthesizes the core arguments surrounding reliability, scalability, and interpretability, framing the debate on whether these models can meaningfully outperform or complement traditional EDA methods. The result is an authoritative overview offering fresh insights into one of today’s most contentious and impactful technology trends.

Though early in its development, quantum computing is now available on real hardware and via the cloud through IBM Quantum. This radically new kind of computing holds open the possibility of solving some problems that are now and perhaps always will be intractable for "classical" computers.

Quantum computing (QC) is fast emerging as a potential disruptive technology that can upend some businesses in the short-term and many enterprises in the long run. Electronic Design Automation (EDA) is uniquely positioned to not only benefit from quantum computing technologies but can also impact the pace of development of that technology. Quantum circuits will play a key role in driving the synergy between quantum and EDA. Much like standard cell libraries became the most important abstraction between CMOS technology and most EDA tooling and spawned four decades of EDA innovation and designer productivity, quantum circuits can unleash a similar streak of innovation in quantum computing.

The design of a high-performance processor in an advanced technology node is a highly concurrent process. While most SoCs are designed with (fairly) stable IP, several trends are driving the design of the micro-architecture, the logic and the physical design of high-performance micro-processors to be an increasingly parallel process. Due to the slowdown of technology progress, a lot more innovation is coming from the micro-architecture. Fast evolving workloads lead to frequent additions of accelerators and instructions. Late security findings drive last minute updates. All these have a significant impact on the logic structure of the design and therefore implications to an efficient physical design. On top of that, when designing in an advanced technology, the technology and its design rules are evolving at the same time. High-performance designs have many memories, register files and caches which are especially susceptible to sometimes small technology rule changes. Even a minimal design rule change can percolate up and have a substantial impact on the floorplan. Fortunately, designers have an unprecedented amount of compute power available to them to conquer the challenges outline above and drive a massive concurrent design process. Especially design teams that harness the vast amount of data coming from the concurrent process can efficiently get to their design goals on time.

As the overall economy and semiconductor industry emerges from one of the worst recessions in years, it is time to take stock of EDA challenges and its future. This panel will focus on which challenges will surge and dominate EDA over the course of next several years and which challenges we can sell short.

With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to reduce both leakage as well as active power in a standard-cell library based high-performance design flow. We will discuss the design and cost issues for using different power saving techniques such as: power gating to reduce leakage, multiple and hybrid threshold libraries for leakage reduction and multiple supply voltage based design. In addition techniques to reduce clock tree power will be presented as power consumed in clocks accounts for a significant portion of total chip power. Practical aspects of implementing these techniques will also be discussed.

Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best power efficiency for high-performance applications. The flexibility of ASICs allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. We explore the trade-off between multiple supply voltages and multiple threshold voltages in the optimization of dynamic and static power. The use of multiple supply voltages presents some unique physical and electrical challenges. Level shifters need to be introduced between the various voltage regions. Several level shifter implementations will be shown. The physical layout needs to be designed to ensure the efficient delivery of the correct voltage to various voltage regions. More flexibility can be gained by using appropriate level shifters. We will discuss optimization techniques such as clock skew scheduling which can be effectively used to push performance in a power neutral way.

Article Share on There is life left in ASICs Authors: Leon Stok IBM TJ Watson Research Center, Yorktown Heights, NY IBM TJ Watson Research Center, Yorktown Heights, NYView Profile , John Cohn IBM Micro-Electronics, Essex-Junction, VT IBM Micro-Electronics, Essex-Junction, VTView Profile Authors Info & Claims ISPD '03: Proceedings of the 2003 international symposium on Physical designApril 2003 Pages 48–50https://doi.org/10.1145/640000.640013Online:06 April 2003Publication History 6citation300DownloadsMetricsTotal Citations6Total Downloads300Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

We present a novel algorithm that applies physical layout information during common subexpression extraction to improve wiring congestion and delay, resulting in improved design closure. As feature sizes decrease and chip sizes increase, the traditional separation of physical design and logic synthesis proves to be increasingly detrimental. Interconnect delay and wiring congestion, among the most critical objective functions to meet design closure, are not considered during logic synthesis. On the other hand, physical design is too deep in the design process to be able to significantly restructure the already technology mapped netlist. While this problem has been addressed previously, the existing solutions only apply simple synthesis transforms during physical design. Hence they are generally unable to reverse decisions made during logic restructuring which have a major negative impact on the circuit structure. In our novel approach, we propose a layout driven algorithm for the concurrent extraction of common subexpressions, one of the most important steps that affect the overall circuit structure, and consequently congestion and wire length during logic synthesis. In addition, we consider dependency relations between cube divisors to improve the extraction process. As a result, our layout driven decomposition algorithm combines logic synthesis and physical layout information to effectively decrease wire length and improve congestion for improved design closure.

In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitioning and clustering algorithms to achieve faster turn around times. With the increasing complexity of designs, the traditional separation of logic and physical design leads to sub-optimal results as the cost functions employed during logic synthesis do not accurately represent physical design information. While this problem has been addressed extensively, the existing solutions apply only simple synthesis transforms during physical layout and are generally unable to reverse decisions made during logic minimization and technology mapping, that have a major negative impact on circuit structure. In our novel approach, we propose congestion aware algorithms for layout driven decomposition and technology mapping, two of the steps that affect congestion the most during logic synthesis, to effectively decrease wire length and improve congestion. In addition, to improve design turn-around-time and handle large designs, we present an approach in which synthesis partitioning and placement clustering co-exist, reflecting the different characteristics of logical and physical domain.

No abstract available.

Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algorithms that minimize a global cost function based on an abstract representation of the design, we decomposed the placement function into a set of transforms and coupled them directly with incremental timing, noise, and/or power analyzers. This coupling results in a direct and more accurate feedback on optimizations for placement actions. These placement transforms are then integrated with traditional logic synthesis transforms leading to a converging set of optimizations based on the concurrent manipulation of boolean, electrical, as well as physical data. Experimental results indicate that the proposed approach creates an efficient converging design flow that eliminates placement and synthesis iteration. It results in timing improvements, and maintains other global placement measures such as wire congestion and wire length. The flexibility of the transformational approach allows us to easily add, extend and support more sophisticated algorithms that involve critical as well as non-critical regions and target a variety of metrics including noise, yield and manufacturability:.

We present a new and innovative logic synthesis approach using regularity information of a design to selectively apply transformations and globally guide the synthesis process. Since traditional logic synthesis applies transformations without consideration of global design characteristics such as regularity and dataflow, it destroys a substantial amount of regular structures. In addition, due to the non-incremental nature of most logic transformations, synthesis relies vastly on the computationally expensive concept of trial and error application of transformations, a time-consuming process in the synthesis of large designs. The proposed approach addresses both shortcomings of traditional logic synthesis and describes a mechanism to speed up logic synthesis and preserve regularity. It selectively applies transformations to places with similar characteristics and to the same stage of a regular structure, introducing a notion of dataflow-aware synthesis. Preservation of regular structures has tremendous advantages to the following physical design stages. It yields high-density layouts, shorter wiring length and improved delay. In addition, the layout becomes more predictable at an earlier design stage.

The wavefront technology mapping algorithm leads to a very simple and efficient implementation that elegantly decouples pattern matching and covering but circumvents that patterns have to be stored for the entire network simultaneously. This coupled with dynamic decomposition enables trade-off of many more alternatives than in conventional mapping algorithms. The wavefront algorithm maps optimally for minimal delay on directed acyclic graphs (DAGs) when a gain based delay model is used. It is optimal with respect to the arrival times on each path in the network. A special timing mode for multi-source nets allows minimization of other (non-delay) metrics as a secondary objective while maintaining delay optimality.

This paper presents an algorithm to select a good set of gate sizes for the primitive gates of a standard cell library. A measurement error on a gate is dened to quantify the discrepancy resulting from replacing the size required by a synthesis sizing algorithm with a size available in a discrete cell library. The criterion for gate size selection is a set of gate sizes that minimizes the cumulative error of a prescribed measurement. Optimal solutions to the gate size selection problem targetting size and delay measurements are presented for cases when the probability distribution and the delay equations are simple. A realistic probability distribution is obtained using a sample space of gates derived fromagroup of designs that is synthesized under the semi-custom synthesis methodology [1]. A \\delay-match " (minimizing delay error) and a \\sizematch" (minimizing size error) set of gate sizes are obtained numerically, and are subsequently realized as discrete cell libraries. The previous group of designs are synthesized using the two selected cell libraries and two other cell libraries, one with \\equal-spacing " of cell sizes and the other with \\exponential-spacing " of cell sizes. The \\size-match " library gives the best overall slack and area results. 1

The effective use of don't cares requires solving several theoretical and practical problems. The theoretical problems are caused by a need to have all tools in a methodology use a consistent semantics of don't cares, so as to guarantee correctness of the final implementation. Several common meanings of "don't care" will be considered, and their respective conditions for design correctness will be derived. The main theoretical result shows that in existing design languages, the following three desirable properties are mutually inconsistent: unrestricted use of non-Boolean values (e.g., X), implementing a large design one partition at a time, and assurance of correctness of the final implementation. A practical solution to this problem involves several issues: specifying don't cares in a language description, deriving them during high-level synthesis, and optimizing logic in their presence. Experimental results showing the impact of don't cares on logic quality are presented.

Retiming is a very promising transformation of circuits which preserves functionality and improves performance. Its benefits are especially promising in automatic synthesis of circuits from higher-level descriptions. However, retiming has not been widely included in current design tools and methodologies. One of the main obstacles is the problem of finding an equivalent initial state for the retimed circuit. In this paper, we introduce a simple modification of the retiming algorithm of Leiserson and Saxe. The modified algorithm helps minimize the effort required to find equivalent initial states and reduces the chance that the network needs to be modified in order to find an equivalent initial state. This algorithm is the kernel of a new efficient retiming method, which searches for optimal retimings while preserving the initial state condition. The paper also presents an improved method to perform the initial state calculation.

This paper describes optimization techniques using don't-care conditions that span the domain of high-level and logic synthesis. The following three issues are discussed: (1) how to describe and extract don't-care conditions from high-level descriptions; (2) how to pass don't-care conditions from high-level to logic synthesis; and (3) how to optimize the logic using don't-care conditions. Efficient techniques are given for these three problems which allow the use of large don't-care sets. Results from several examples demonstrate that these techniques are very effective for both area and delay minimization.

It is commonly expected that any correct implementation can replace its specification inside a larger design without violating the correctness of the whole design. This property (called replaceability) is automatically satisfied in the absence of don't cares because "correctness" by definition implies that specification and implementation compute the identical function. However don't cares allow an implementation to compute a different function, and thus make it difficult to ensure replaceability. Whether this problem occurs depends on the exact meaning of "don't care" and the associated definition of "correctness". We will consider three meanings of "don't care" and for each give conditions under which correct implementations may replace their specifications.

The effects of false loops caused by resource sharing are described. When a separate controller and data path are constructed, two types of false loops can be distinguished: the ones that go through the controller and the ones that loop around in the data path. A model to detect both types of loop during the resource sharing phase is described. Based on this model an algorithm which prevents false loops in the combinatorial network to be constructed, while maintaining as much freedom as possible for the resource sharing, is described. Experiments show that the loop-free data-paths do not need more functional units than the ones that contain false loops.>

A multiplier structure is described which leads to a very efficient implementation in a module generator environment. The structure, a block-multiplier, features a wide range of area-time tradeoffs maintaining efficiency. The structure makes it possible to implement a fully serial or a fully parallel multiplier and many combinations in between. A new concept for the carry-hold circuitry plays a key role. The theoretically derived formulas which describe the relations between the area, timing, and bitwidth of this multiplier structure are verified by a large number of experiments.>

In this paper a computer program for the construction of a schematic diagram (the artwork) from a net list (the network) is presented. The network-to-artwork generator is composed of a separate placement (Pablo) and a routing part (Eureka). For both parts algorithms, following guidelines traditionally used in manual drawing of schematic diagrams, are used. Several examples are shown and some data on the speed of the algorithms are listed.