In this paper, a rapid binary search-based calibration method for capacitor mismatch errors in CDAC structures is proposed. Limitations of existing methods, such as the need for ADC architecture modifications, long convergence times, and high design complexity, are addressed by this approach. By employing a simple binary search algorithm, capacitor weights are quickly optimized to maximize the SNDR, effectively calibrating capacitor mismatch errors. The implementation of this method is relatively straightforward, with comparatively low computational resource requirements, offering strong flexibility. Simulation results for a 14-bit Pipelined-SAR ADC model indicate that, after calibration, average SNDR and SFDR improvements of 8.74 dB and 20.65 dB, respectively, were achieved.

This article introduces a successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a foreground capacitor mismatch self-calibration method. The proposed floating operation puts the uncalibrated high-bit capacitor into the floating state, preventing the sub-ADC from saturating caused by comparator static offset during the calibration process. To address the random mismatch of the LSB capacitors and improve the calibration accuracy, this article employs round-robin grouping of eight sets of LSB capacitors. In addition, a precharged bootstrapped switch is proposed to achieve high sampling linearity with low power consumption and area overhead. An anti-interference custom-designed 0.5-fF capacitor structure is suggested for binary-weighted capacitor mismatch of capacitive DAC (CDAC). Furthermore, the circuit implementation of the comparator utilized by ADC is also discussed. The prototype was fabricated in a 180-nm CMOS process with a 1.8-V supply and achieved spurious-free dynamic ranges of 108.9 and 92.38 dB at an input frequency of 1 kHz while operating at sampling rates of 100 kS/s and 1 MS/s, respectively. The prototype consumes 6.745 mW and occupies 0.91$\text {mm}^{2}$.

This article presents a 1.5–4-GHz transmitter with a reconfigurable 10–200-MHz signal bandwidth, supporting multiband in 5G new radio (NR). A fully differential operational amplifier (OPA) with novel capacitor-coupled feedforward compensation is proposed to support broadband analog baseband (ABB) with enhanced efficiency and linearity. The linear-in-dB gain control method, utilizing the thermometer code and the reusable resistor block (RB), is proposed to ensure accurate and monotonic gain control. The proposed two-stage push–pull power driver amplifier (PDA), covering the 1.5–4-GHz range, employs an efficiency-enhanced on-chip transformer and switched-capacitor arrays to support broadband operation. Designed using a CMOS large-signal (LS) nonlinear model and the$\mathrm {G}_{\mathrm {3}}$fluctuation method, the complementary PDA extends the linear operating range, mitigates AM–PM distortion, and improves efficiency. Moreover, the matching network is systematically analyzed to achieve the most efficient power transfer and load matching. To compensate for the dc offset caused by process, voltage, and temperature (PVT) variations, as well as the dc level mismatch between ABB stages, both digital dc offset calibration circuits and an analog level shifter are integrated on-chip. The transmitter is implemented in 55-nm CMOS with a 1.8/2.5-V power supply and a core chip area of$\text {2.99 mm}^{2}$. The transmitter achieves S22 output matching below −12 dB across the 1.5–4-GHz frequency range and provides a 36-dB gain range with a 0.375-dB step. The measured error vector magnitude (EVM) for the NR40MHz signal is 1.67% at 4.2-dBm average output power in n41 and 1.54% at 3.7-dBm average output power in n78, with corresponding adjacent channel power ratio (ACPR) of −48.75 and −48.067 dBc, respectively.

This paper introduces a 0.5-V, two-stage, pseudo-differential bulk-driven operational transconductance amplifier with high gain and linearity for low-power continuous-time applications. The input stage’s common-mode feedback utilizes a linear resistor detector with a conductance reduction cross-coupled pair to mitigate the loading effect of the common-mode detector resistor at ultra-low power operations. Temperature dependence of the conductance reduction circuit is compensated. The impact of the conductance reduction circuit on linearity performance is explored. The output stage employs a class-AB topology and utilizes a phase lead compensator to stabilize the OTA. Implemented in 180 nm CMOS technology, this OTA achieves a DC gain and slew rate of 68 dB and 26.1 V/$\mu $s, respectively, under a capacitive load of 10 pF. The total power consumption is$34.2~\mu $W. With unit gain feedback configuration, the measured total harmonic distortion is only 0.02% at an output amplitude of 500 mVpp. Test results validate the proposed circuit, positioning it competitively compared to state-of-the-art designs.

The performance of zero intermediate frequency (IF) receiver is usually limited by the frequency dependent I/Q mismatch, which gets worse with the increase of the signal bandwidth. Because the frequency dependent errors caused by the mixer and the baseband filters are difficult to eliminate, digital calibration methods are widely adopted. Among all the calibration methods, the algorithm based on the detection in frequency domain is able to extract the error at different frequencies which makes it suitable for foreground calibration. This paper proposed a receiver I/Q mismatch calibration method applied to wideband FDD transceivers, which can extract the error in frequency domain by transmitting customized signals through transmitters. A reasonable frequency plan is adopted to avoid the interference of TX image, nonlinearity and LO leakage and the wideband I/Q mismatch is compensated by a complex finite impulse response (FIR) filter. The proposed algorithm fully utilizes the existing hardware of the receiver, achieving a good balance between algorithm performance and hardware cost, which is validated on a FDD transceiver platform and the image rejection ratio (IRR) is improved from 33dB to at least 66dB in the whole baseband with a bandwidth of 245MHz.

This paper presents a reconfigurable 4.75-to-32 GBuad transmitter (TX) that operates up to 64Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 32Gb/s with non-return-to-zero (NRZ) modulation scheme, designed in the 28-nm CMOS technology. The TX incorporates a quarter-rate architecture with a tap coefficient flexible feed-forward equalizer (FFE) up to 3 FFE taps. The TX employs a tailless CML driver with common-mode feedback (CMFB) for output swing control which provides 0.8 V pp output swing, and a helical wiring T -coil for bandwidth expansion. The clock path of the TX includes the duty-cycle detection/correction (DCD/DCC) circuits with a resolution of sub-60fs and quadrature-error detection/correction (QED/QEC) circuits, and a LC phase locked loop (PLL) with a local injection-locked (IL) quadrature clock generation circuit. The TX operating at 64 Gb/s in PAM-4 modulation consumes 76.7 mW from 1-V supply with 0.8 V pp, achieving an 1.2 pJ/b energy efficiency. The TX front end occupies an active area of 0.063 mm2.

This paper presents a foreground calibration technique with LSB capacitors for an 18-bit SAR ADC. Calibration using LSB capacitors suffers from poor accuracy owing to the comparator static offset and the random mismatch in LSB capacitors. The proposed floating capacitors operation addresses the miscalibration due to the saturation of sub-ADC resulting from the static offset. In addition, calibration using multiple groups of LSB capacitors is taken for each capacitor measurement to average out the effect of random mismatch in LSB capacitors, which improves the calibration accuracy effectively. Behavioral simulations of an 18-bit SAR ADC demonstrate the availability and robustness of the proposed calibration techniques.

In this paper, a novel foreground calibration method for wideband zero IF receiver I/Q mismatch is proposed based on frequency domain feature extraction, which is suitable for the FDD transceiver integrated with digital signal processing modules. The proposed algorithm calibrates the frequency dependent mismatch through a complex digital FIR filter, and uses the transmitter as the signal source. A frequency allocation scheme is applied to avoid the interference from the transmitter image component. Mismatch factors such as LO phase and amplitude mismatch and baseband transfer function mismatch can be calibrated together directly by this method, which eliminates the error accumulation caused by multi-level cascade calibration. Finally, a high image rejection ratio is obtained, and the image component power is stably compressed below the quantization noise power in the whole baseband.

Nyquist current-steering DACs often employ half-rate interleaved topology to obtain ultra-high sampling rate in wideband communication systems. As a deterministic timing error, duty cycle error is a main factor to cause performance degradation in half-rate DACs. The limited output bandwidth caused by large parasitic capacitance further restricts the dynamic linearity. The paper mathematically analyzes the duty cycle error in half-rate DACs based on Heaviside function and a close-form expression of signal-to-distortion ratio (SDR) is derived under the influence of limited output bandwidth. The paper theoretically demonstrates that the duty cycle error causes distortion at frequency of fs/2-fin and it gets worse near Nyquist frequency under impact of the limited bandwidth.

A 6-bit current-steering DAC in 40nm CMOS is presented for wideband communication systems. Owing to the proposed true single phase clock (TSPC) dynamic pipelined decoding logic, the DAC achieves sampling rate beyond 10GS/s in an optimized 4-2 segmentation without time interleaving. The unit cell layout including switch transistors, cascode transistor and current source is compacted to reduce parasitic capacitance and maintain high output impedance for wideband linearity. The proposed one-dimension (1-D) current source array (CSA) together with trunk output distribution enhances output bandwidth further. The DAC obtains spurious free dynamic range (SFDR) > 30dB over the entire Nyquist range at 12GS/s sampling rate. The core occupies the area of 0.035mm2and consumes 110mW of power from 1.1V supply voltage.

This paper presents the radar scattering phenomenology of arctic shallow lake ice. This is an important feature for monitoring the arctic climate for this purpose, a full-wave simulation model to analyze lake ice scattering that includes columnar air bubbles and rough interface is presented. The proposed model can handle complex interactions between high density air bubbles and rough ice surfaces. Based on this model, the scattering contributions from the rough ice/water interface and columnar air bubbles in the ice at C band are calculated. It is concluded that the roughness at the interface between ice and water is the dominate contributor to the observed backscatter.

Polarimetric synthetic aperture radar satellite and ground-based Ku- and X-band scatterometer measurements are used to explore the scattering mechanism for ice in shallow Arctic lakes, wherein strong radiometric responses are seen for floating ice, and low returns are evident where the ice has grounded. Scatterometer measurements confirm that high backscatter is from the ice/water interface, whereas polarimetric decomposition suggests that the dominant scattering mechanism from that interface is single bounce. Using Fresnel equations, a simple model for surface bounce from the ice/water interface is proposed, and its predictions are supported by experimental parameters such as co-pol phase difference, co-pol ratio, and the results of rigorous numerical modeling. Despite early research suggesting double-bounce scattering from columnar air bubbles and the ice/water interface as the dominant scattering mechanism in shallow lakes, this paper strongly supports a single-bounce model.

In this paper we present a medium frequency (MF) band imaging system to estimate the sub-surface hydraulic fractures. We propose a helical dipole antenna for the borehole imaging application. The proposed antenna is loaded with a ferrite-bundle and is optimized to achieve an ultra-compact size to fit within a volume of λ0/1400 × λ0/1400 × λ0/35 while maintaining a relatively high efficiency of about 20%. The feeding network is designed to match the antenna input impedance with the frequency tunability. Based on the proposed antenna, a radio-wave technique for detecting fractured regions in subsurface rock layers is developed. Compared with conventional high frequency mapping system, the penetrating distance has increased to kilometers range due to the low propagation loss at MF band. The method is based on single-hole setup with separate transmitter and receiver antennas. The time-gating is performed to minimize the direct-link signals. Post-processing maps the conductivity contrast in the target area with a good resolution.

In this paper we present a radio technique for detecting and measuring the extent of hydraulic fractures in subsurface rock layers using MF band. The method is based on transmission measurements among elements of vertical and horizontal arrays in the borehole before and after fracking process. To realize this system a novel super-miniaturized borehole antenna operating at 2MHz is also presented. The proposed antenna is based on a ferrite-loaded helical dipole antenna optimized to fit a volume λ0/1337 × λ0/1337 × λ0/80 while maintain a high radiation efficiency of about 10%.

Wavelet packet-division multiplexing (WPDM) is a high-capacity, flexible, and robust multiple-signal transmission technique in which the message signals are waveform coded onto wavelet packet basis functions for transmission. We derive an expression for the probability of error for a WPDM scheme in the presence of both impulsive and Gaussian noise sources and demonstrate that WPDM can provide greater immunity to impulsive noise than both a time-division multiplexing scheme and an orthogonal frequency-division multiplexing scheme.