This paper presents an overview of the Internet of Things (IoT) device design and simulation, with a specific focus on low-power design principles - everything in the context of the LoLiPoP-IoT project. The project aims to enhance IoT device usability by reducing maintenance requirements related to battery recharging or replacement. Another key goal is to significantly decrease the massive waste generated by discarded primary batteries, contributing to more sustainable and user-friendly IoT solutions for the future. The primary focus of this paper is on a custom IoT localization tag, for which we simulate solar cells - ranging from basic modeling to their integration into electrical circuits - and the power consumption of the tag's electronics platform. The analyzed sample platform is built on the nRF52833 microcontroller and the DW3110 ultra-wideband transceiver. We also applied our experimental framework principles to optimize power consumption and extend battery life. Reductions in photovoltaic panel area were achieved for both devices with a 5-year lifespan and fully autonomous tags, though with increased localization latency. Furthermore, this paper demonstrates how IoT devices, including their firmware, can be effectively modeled and simulated using publicly available tools.

The increasing interest in IoT devices poses significant challenges in battery waste, not to mention the effort needed to replace the batteries in remote applications. In the LoLiPoPIoT project, we address these issues by developing energy-efficient IoT platforms that extend the device’s battery life through lowpower design and energy harvesting. However, for a successful design, preliminary measurements and simulations need to be done to demonstrate the feasibility of the utilized technologies and their dimensioning. This paper presents a method of collecting data and creating a novel portable simulation model implemented in a Microsoft Excel spreadsheet. During the data collection phase, we plot detailed energy consumption and income of our device (i.e., asset tracking tag). PC1D simulations of a crystalline-silicon photo-voltaic panel and the device model were utilized to collect data for the final (i.e., composed) model. Our model allows real-time adjustments of key parameters, such as ambient light intensity, battery capacity, and photo-voltaic panel sizing. Our goal is to deliver a solution that allows our partner to conduct basic experiments on their own computers with a user-friendly interface for parameter selection and result visualization. Our results indicate that for one application area, a $25 \mathrm{~cm}^{2}$ photovoltaic panel is needed, while for the other, a $23 \mathrm{~cm}^{2}$ panel is enough.

The LoLiPoP-IoT project aims to pioneer Long Life Power Platforms for IoT to extend battery life, minimize maintenance, and facilitate installation within existing environments. With a focus on supporting an inclusive ecosystem of developers, integrators, coordinators, and users, the project's Grand Objectives encompass a range of aims, including providing long-lasting battery solutions, reducing battery waste, enhancing asset tracking and predictive maintenance, and improving energy efficiency in buildings. These objectives are realized through nine selected practical applications across three primary domains: Asset Tracking, Condition Monitoring and Predictive Maintenance, and Energy Efficiency and Comfort in Buildings. Expected impacts of the LoLiPoP-IoT project include significantly extended battery life, reduced maintenance overhead, decreased costs associated with asset location, improved asset management efficiency, enhanced building comfort with reduced energy consumption, and substantial revenue generation for industry partners. The project's strategic objectives are notably harmonized with key EU initiatives outlined in the Green Deal, Circular Economy, and the New Industrial Strategy for Europe.

Many researchers shown that approximate circuits are able to provide a new perspective on the development of electronic systems. Mostly, they tried to find an optimal trade-off between the approximation error and resource savings for predefined applications. However, they used to concentrate mainly on design aspects regarding relaxed functional requirements, but neglected aspects like timing, sequential/asynchronous nature of circuits, uncertainty due to process/parameter variations, excessively high operating frequencies or low voltages. This paper aims to take a step ahead by moving towards the verification of dynamic properties of systems based on approximate circuits, with a focus on sequential/asynchronous circuits and uncertainty. First, the paper presents our approach to modeling approximate systems by means of stochastic hybrid timed automata. Then, it shows the principle/advantage of verifying properties of modeled systems by the so-called statistical model checking technique. Further, it presents a framework that takes at its input the model of an accurate system, its timing and other requirements and expected properties, information about basic building blocks and acceptable cost/quality trade-off to produce an approximated system that meets the requirements maximally and satisfies the properties. Finally, the paper evaluates our approach and outlines future research perspectives.

Narrow timing margins in modern digital circuits result in delay defects that are difficult to detect. The probability that such a defect occurs increases with factors such as shrinking feature sizes, increasing process variations, operating frequencies, and aging/stress of the circuits. Traditionally, timing is considered in connection with the logic design, physical design and layout, and delay testing phases of the circuit development process and builds on principles of delay characterization, fault models and timing analysis. This paper presents a model checking approach aiming to facilitate the solutions of problems with regard to analyzing consequences and testing of delay faults. Our approach expects that a circuit is modeled as a network of stochastic hybrid timed automata capable to describe the circuit both in the logical and temporal domains, including facts such as uncertainty and variations. In our approach, we gather attributes and formalize expected properties of a circuit and transform the circuit into our model. Then, we use a statistical model checker to check the properties and to produce a counter-example for each property being violated. Further, we transform the counter-examples into test cases and finally, into a delay test able to check whether the timing requirements are met.

Many works have shown that approximate circuits may play an important role in the development of resource-efficient electronic systems. This motivates many researchers to propose new approaches for finding an optimal trade-off between the approximation error and resource savings for predefined applications of approximate circuits. The works and approaches, however, focus mainly on design aspects regarding relaxed functional requirements while neglecting further aspects such as signal and parameter dynamics/stochasticity, relaxed/non-functional equivalence, testing or formal verification. This paper aims to take a step ahead by moving towards the formal verification of time-dependent properties of systems based on approximate circuits. Firstly, it presents our approach to modeling such systems by means of stochastic timed automata whereas our approach goes beyond digital, combinational and/or synchronous circuits and is applicable in the area of sequential, analog and/or asynchronous circuits as well. Secondly, the paper shows the principle and advantage of verifying properties of modeled approximate systems by the statistical model checking technique. Finally, the paper evaluates our approach and outlines future research perspectives.

Ideally, the reliability can be assessed analytically, provided that an analytical solution exists and its presumptions are met. Otherwise, alternative approaches to the assessment must apply. This paper proposes a novel, simulation based approach that relies on stochastic timed automata. Based on the automata, our paper explains principles of creating reliability models for various scenarios. Our approach expects that a reliability model is then processed by a statistical model checking method, used to assess the reliability by statistical processing of simulation results over the model. Main goal of this paper is to show that instruments of stochastic timed automata and statistical model checking are capable of facilitating the assessment process even for adverse conditions such as bathtub shaped failure rates.

The problem of dependability assessment can be solved analytically just under predefined conditions. If they do not hold, alternative approaches must apply. Widely, they rely on the Monte Carlo simulation, suffering by the high computational complexity. Some rest on further instruments such as probabilistic timed automata that have been shown to be efficient to solve problems in various areas. However, more general as well as precise and faster instruments such as stochastic timed automata (STA) and statistical model checking (SMC) are available for the same purpose the moment. In the paper, basic terms and principles behind the construction of reliability models and dependability assessment on the STA/SMC basis are summarized, followed by a demonstration of their practical applicability in the area of non-repairable systems. Our main goal is to show that, instruments of STA/SMC can facilitate the dependability assessment process even in adverse conditions such as presence of multiple faults of various parameters.

In this paper, an overview of scheduling mechanisms constructed to enhance availability of services an embedded real-time system delivers is introduced along with the concept of a framework for comparison of the mechanisms. The framework expects that XML-based descriptions of the following parts of the system are available at its input: target device, operating system, application, scheduler and specification of experiments. On basis of the inputs, the framework is able to produce source-codes for a given platform and an operating system and after their compilation and programming by third-party tools, to perform and evaluate the experiments according to their specification. The applicability of the framework has been shown on selected component-of-the-shelf components such as a microcontroller, an operating system and on several sets of artificial as well as real-world applications running under limiting conditions such as insufficient amount of power and/or computational (re)sources. At the end of the paper, several mechanisms are evaluated on basis of the framework in order to show its practical applicability and kind of results achievable at its output.

The paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hardware is designed to pre-process all interrupts before they arrive to the system. Then, the hardware is able to buffer each interrupt-related communication until the system is underloaded or running an activity having a lower priority comparing to the interrupt. Design of the hardware was described in VHDL and synthesized into Xilinx Spartan-6 devices. Details such as buiding blocks, overheads and limits related to the realization are presented in this paper.

In the paper, a concept and an early analysis of an embedded hardware/software architecture designed to prevent the software from both timing disturbances and interrupt overloads is outlined. The architecture is composed of an FPGA (MCU) used to run the hardware (software) part of an embedded application. Comparing to previous approaches, novelty of the architecture can be seen in the fact it is able to adapt interrupt service rates to the actual software load being monitored with no intrusion to the software. According to the actual software load it is able to buffer all interrupts and related data while the software is highly loaded and redirect the interrupts to the MCU as soon as the software becomes underloaded.

Embedded systems as well as real-time kernels for their construction are sensitive to transient and other faults, each of which can lead to various errors at various system levels and can potentially result in the system failure. In existing works, sensitivity to transient SEU errors was studied only with the goal to classify SEU impacts to the system behavior. In this paper, the study is extended to permanent faults being injected into the persistent memory used to store the program and into the volatile memory used to store data structures. Moreover, it is studied there how the sensitivity is affected if combination of selected software-implemented fault tolerant techniques is built into the kernel and task levels of the system. The set of common fault tolerant techniques is extended to a novel watchdog-inspired technique designed to check the correctness of task executions. On the experimental basis, it is shown that the fault impacts can be softened by the proper combination of the techniques.

Major drawback of high level design methodologies such as RTL can be seen in the following facts. First, they lack of sufficiently precise fault models - compared to sophisticated models available for low level description levels such as logic gate level. Second, since the structure of a design changes significantly with every logic synthesis run, testability analysis is typically performed only after final logic synthesis. As a consequence, results of the analysis could be obtained when it is very costly to reflect them in the high level design. The drawbacks can be removed in several ways. In the contribution, it is supposed the analysis is performed at RTL and is efficient enough to be run after each change in RTL design - giving a designer an immediate information about the change impact to testability parameters. Under the assumption, low computational complexity and accuracy are the requirements posed to the analysis. The latter requirement is met if strong correlation is detected between RTL testability analysis results and low-level test pattern generation results. In the paper, it is shown such a correlation exists although relatively simple academic RTL testability analysis solution is compared to widely used commercial gate-level test pattern generation solution. Detail results achieved during the experiments over scan circuits are presented, discussed and summarized in the paper.

In the paper, novel method for reducing power dissipation during test application time is presented. When compared to existing methods, its advantage can be seen in the fact that power dissipation is evaluated by means of precise and fast simulation based metric rather than by means of commonly utilized simple metric based on evaluating Hamming distance between test vectors. In our method, the metric is evaluated over CMOS primitives from AMI technological libraries. In order to reduce power dissipation, the sequence of test vectors to be applied and proper ordering of registers within scan chains are optimized. In existing approaches, the optimizations are typically performed separately in a sequence because problems they correspond to are seen to be independent. On contrary to that, we have united the search spaces and solved these two problems as a single optimization task. Genetic algorithm operating over an appropriate encoding of the problem was utilized to optimize the problem. Proposed method was implemented in both single and multiprocessor environments and it was successfully tested to cooperate with commercial tools. At the end of the paper, results achieved over benchmarks from ISCAS85, ISCAS89 and ITC99 sets are presented and compared to results of existing methods.

In most of existing approaches, the reorganization of test vector sequence and reordering scan chains registers to reduce power consumption are solved separately, they are seen as independent procedures. In the paper it is shown that a correlation between these two processes and strong reasons to combine them into one procedure run concurrently exist. Based on this idea, it is demonstrated that search spaces of both procedures can be combined together into a single search space in order to achieve better results during the optimization process. The optimization over the united search space was tested on ISCAS85, ISCAS89 and ITC99 benchmark circuits implemented by means of CMOS primitives from AMI technological libraries. Results presented in the paper show that lower power consumption can be achieved if the correlation is reflected, i.e., if the search space is united rather than divided into separate spaces. At the end of the paper, results achieved by genetic algorithm based optimization are presented, discussed and compared with results of existing methods.

Testability is one of the most important factors that are considered during design cycle along with reliability, speed, power consumption, cost and other factors important for a customer. Estimation of testability parameter strongly depends on how accurate information utilized for the estimation by a testability analysis method is. In the paper, two results of our previous, long-term research in the area of digital circuit testability analysis are summarized: principle of our testability analysis engine and libraries used to store the information outgoing from transparency models. The engine is general and accuracy of its results strongly depends on the information stored in the libraries. If simple transparency model is utilized, information about circuit testability could be far away from real state of the circuit. Otherwise, testability information can approximate so serious parameter such as fault-coverage factor.

In the paper, a method for test controller synthesis based on testability analysis results is presented. The proposed method enables to create a finite state machine with output, which can control all enable, address and clock inputs of elements in the circuit during the test application process. Proposed testability analysis method is efficient for RT level pipelined data-path circuit. Close coupling of testability analysis and test controller synthesis saves the test cost in terms of area overhead, test time and fault coverage. All processes are described formally.

In the paper a method for estimation the circuit testability on the Register Transfer Level (RTL) is presented. The method allows to perform fast testability estimation in linear time complexity (regarding the number of components and interconnects of the circuit). Proposed approach is based on utilization of controllability and observability measurement for estimation of overall circuit testability. The application of developed method is demonstrated in a software tool for the development of RTL benchmark circuits with predefined testability properties. The results gained by our testability analysis method are compared with the results of professional ATPG tool. Experiments show the good correlation of the results obtained by our method and professional ATPG tool with significantly lower time complexity when our algorithm is used.

In the paper, the principles of scan educational tool are presented. First, the motivation for this activity is briefly mentioned. Then, the structure of software package together with the principles of communicating and controlling the tools belonging to the system are explained. It is shown how the system can be utilized for testability analysis and design for testability demonstrations resulting in applying scan design principles in the design.

The paper proposes two approaches to test scheduling. The first one utilizes the concept of TACG (Test Application Conflict Graph). For the testing process the resource utilization model is defined and used for the TACG construction. Different conflicts that must be taken into account during test scheduling are presented. The paper offers a methodology that can be utilized during embedded test design process, the final goal of which is to reduce the overall test application time and power consumption during the test application. The second methodology is based on optimising the test schedule - the test application time, TAM width and power consumption are taken into account during the process. The goal of the methodology is a reasonable trade-off between these parameters.

In the paper a new heuristic approach to the RTL testability analysis is presented It is shown how the values of controllability/observability factors reflecting the structure of the circuit and other factors can be utilised to find solutions which are sub-optimal but still acceptable for the designer. The goal of the methodology is to enable the identification of such testability solutions which satisfy concrete requirements in terms of the number of registers included into the scan chain, the area overhead and the test application time as a result of RTL testability analysis. The approach is based on the combination of analytical and evolutionary approaches at the RT level.