We present an integrated circuit fabricated in a process co-integrating CMOS and hafnium-oxide memristor technology, which provides a prototyping platform for projects involving memristors. Our circuit includes the periphery circuitry for using memristors within digital circuits, as well as an analog mode with direct access to memristors. The platform allows optimizing the conditions for reading and writing memristors, as well as developing and testing innovative memristor-based neuromorphic concepts.

The deployment of Edge AI requires energy-efficient hardware with a minimal memory footprint to achieve optimal performance. One approach to meet this challenge is the use of Binary Neural Networks (BNNs) based on non-volatile in-memory computing (IMC). In recent years, elegant ReRAM-based IMC solutions for BNNs have been developed, but they do not extend to the first layer of a BNN, which typically requires non-binary activations. In this paper, we propose a modified first layer architecture for BNNs that uses k-bit input images broken down into k binary input images with associated fully binary convolution layers and an accumulation layer with fixed weights of$2^{-1}, \ldots, 2^{-k}$. To further increase energy efficiency, we also propose reducing the number of operations by truncating 8-bit RGB pixel code to the 4 most significant bits (MSB). Our proposed architecture only reduces network accuracy by 0.28% on the CIFAR-10 task compared to a BNN baseline. Additionally, we propose a cost-effective solution to implement the weighted accumulation using successive charge sharing operations on an existing ReRAM-based IMC solution. This solution is validated through functional electrical simulations.

Bayesian reasoning is a machine learning approach that provides explainable outputs and excels in small-data situations with high uncertainty. However, it requires intensive memory access and computation and is, therefore, too energy-intensive for extreme edge contexts. Near-memory computation with memristors (or RRAM) can greatly improve the energy efficiency of its computations. Here, we report two fabricated integrated circuits in a hybrid CMOS-memristor process, featuring each sixteen tiny memristor arrays and the associated near-memory logic for Bayesian inference. One circuit performs Bayesian inference using stochastic computing, and the other uses logarithmic computation; these two paradigms fit the area constraints of near-memory computing well. On-chip measurements show the viability of both approaches with respect to memristor imperfections. The two Bayesian machines also operated well at low supply voltages. We also designed scaled-up versions of the machines. Both scaled-up designs can perform a gesture recognition task using orders of magnitude less energy than a microcontroller unit. We also see that if an accuracy lower than 86.9% is sufficient for this sample task, stochastic computing consumes less energy than logarithmic computing; for higher accuracies, logarithmic computation is more energy-efficient. These results highlight the potential of memristor-based near-memory Bayesian computing, providing both accuracy and energy efficiency.

Today computing centric von Neumann architectures face strong limitations in the data-intensive context of numerous applications, such as deep learning. One of these limitations corresponds to the well known von Neumann bottleneck. To overcome this bottleneck, the concepts of In-Memory Computing (IMC) and Near-Memory Computing (NMC) have been proposed. IMC solutions based on volatile memories, such as SRAM and DRAM, with nearly infinite endurance, solve only partially the data transfer problem from the Storage Class Memory (SCM). Computing in SCM is extremely limited by the intrinsic poor endurance of the Non-Volatile Memory (NVM) technologies. In this paper, we propose to take the best of both solutions, by introducing a Computing Row Buffer (C-RB), using a Computing SRAM (C-SRAM) model, in place of the standard Row Buffer (RB) in the SCM. The principle is to keep operations on large vectors in the C-RB of the SCM, minimizing data movement to and from the CPU, thus drastically reducing energy consumption of the overall system. To evaluate the proposed architecture, we use an instruction accurate platform based on Intel Pin software. Pin instruments run time binaries in order to get applications' full memory traces of our solution. We achieve energy reduction up to 7.9x on average and up to 45x for the best case and speedup up to 3.8x on average and up to 13x for the best case, and a reduction of write accesses in the SCM up to 18 %, compared to SIMD 512-bit architecture.

Phase change memory (PCM) device associated with Ovonic Threshold Switch (OTS) selector is a proven solution to fill the gap between DRAM and mass storage. This technology also has the potential to be embedded in a high-end microcontroller. However, programming and reading phases efficiency is directly linked to the selector’s leakage current and the sneak-path management. To tackle this challenge, we propose in this paper, a new sense amplifier able to generate an auto-reference taking into account leakage current of unselected cell, including a regulation loop to compensate voltage drop due to reading current sensing. This auto-referenced sense, built on the charge-sharing principle, is designed on a 28nm FDSOI technology and validated through extensive Monte-Carlo and corner cases simulations. From the simulation results, our sense amplifier is demonstrated to be robust for an ultra-large range of sneak-path current and consequently for a large range of memory array size, suitable for embedded memory in high-end microcontroller.

The design of systems implementing low precision neural networks with emerging memories such as resistive random access memory (RRAM) is a significant lead for reducing the energy consumption of artificial intelligence. To achieve maximum energy efficiency in such systems, logic and memory should be integrated as tightly as possible. In this work, we focus on the case of ternary neural networks, where synaptic weights assume ternary values. We propose a two-transistor/two-resistor memory architecture employing a precharge sense amplifier, where the weight value can be extracted in a single sense operation. Based on experimental measurements on a hybrid 130 nm CMOS/RRAM chip featuring this sense amplifier, we show that this technique is particularly appropriate at low supply voltage, and that it is resilient to process, voltage, and temperature variations. We characterize the bit error rate in our scheme. We show based on neural network simulation on the CIFAR-10 image recognition task that the use of ternary neural networks significantly increases neural network performance, with regards to binary ones, which are often preferred for inference hardware. We finally evidence that the neural network is immune to the type of bit errors observed in our scheme, which can therefore be used without error correction.

This paper presents a new methodology for automating the Computational SRAM (C-SRAM) design based on off-the-shelf memory compilers and a configurable RTL IP. The main goal is to drastically reduce the development effort compared to a full-custom design, while offering a flexibility of use and a high-yield production. The proposed C-SRAM architecture has been developed to process energy-efficient vector data coupled with a scalar processor, while limiting the data transfer on the system bus. The results obtained by post P&R simulations show that 2RW and 4RW C-SRAM configurations using the double pumping technique achieved the highest performance to process vectorized MAC operations compared to the others configurations. Moreover, it has been shown that the impact of the digital wrapper decoding and executing the instructions can be mitigated by increasing the memory cut size to represent less than 10% in area and 20% in power consumption.

The advent of deep learning has considerably accelerated machine learning development. The deployment of deep neural networks at the edge is however limited by their high memory and energy consumption requirements. With new memory technology available, emerging Binarized Neural Networks (BNNs) are promising to reduce the energy impact of the forthcoming machine learning hardware generation, enabling machine learning on the edge devices and avoiding data transfer over the network. In this work, after presenting our implementation employing a hybrid CMOS - hafnium oxide resistive memory technology, we suggest strategies to apply BNNs to biomedical signals such as electrocardiography and electroencephalography, keeping accuracy level and reducing memory requirements. We investigate the memory-accuracy trade-off when binarizing whole network and binarizing solely the classifier part. We also discuss how these results translate to the edge-oriented Mobilenet V1 neural network on the Imagenet task. The final goal of this research is to enable smart autonomous healthcare devices.

Integrated Circuits (ICs) have to be protected against threatening environmental radiations and malicious perturbations. A large panel of countermeasures has been developed to answer the needs of this challenging field. The Bulk Built-In Current Sensor (BBICS) is a highly reliable solution for the detection of these abnormal transient radiations that could induce a transient current in the Front-End of Line (FEoL). This paper proposes an innovative sensor based on the BBICS associated to the power-efficient emerging non-volatile memory Spin Transfer Torque Magnetic Random Access Memory (STTMRAM). The goal of this security solution is to detect both possible photoelectrical laser injections and thermal perturbations. Thus, the proposed architecture designated by Dual Detection of Heating and Photocurrent attacks (DDHP) highlights a dual detection efficiency, on the CMOS circuitry and on the Back-End of Line (BEoL) STT-MRAM technology.

Internet of Things (IoT) applications deployment relies on low-power circuits. Nowadays, on top of power consumption, security concern has become a real issue. Light-Weight Cryptography (LWC) has been developed to answer this challenge. In the lightweight cryptographic landscape, the PRESENT algorithm exhibits low power and small area features. At the same time, emergent resistive memory technologies such as Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) seem to be a strong candidate for Flash replacement with advanced design features such as hybridization with CMOS. In this context, we propose a hybrid CMOS/STT-MRAM technology for PRESENT cryptographic circuit for normally-off IoT applications. We demonstrate that the hybrid implementation is more power-efficient than the CMOS implementation when switched off for a period longer than 49.1 ms for a 180 nm CMOS core process with an area overhead of ×7. Based on this result, trends down to 28 nm node are studied and lead to outstanding performances with a power-effeciency of the hybrid version reached after 185 μs standby mode. In this scenario, an energy of 6,1 pJ is sufficient to store data in the Non-Volatile Flip-Flops (NVFFs) with a reduced area overhead of ×0.23.

The Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has been identified, by the International Technology Roadmap for Semiconductors (ITRS), as one of the most promising emerging technology. Different works handled the retention and reliability of STT-MRAM. However, to the best of our knowledge, the impact of a pulsed laser beam on STT-MRAM reliability and security has not been investigated so far as proposed in this paper. Since STT-MRAM are Back-end Of Line devices, we exposed the bit cells from the front-side to a 1064 nm wavelength laser pulse. The devices are electrically characterized (switching conditions between the two logical states) before and after the laser irradiation. The main result of this study is the demonstration of a resistance switching from Anti-Parallel (AP) to Parallel (P) state after the laser irradiation. That is how data integrity was altered by this irradiation, flipping the bit stored in this memory.

The emergence of non-volatile random access memory technologies, such as resistive and spintronic RAMs are triggering intense interdisciplinary activity. These technologies have the potential of providing many benefits, such as energy efficiency, high integration density, CMOS-compatibility, re-configurability, non-volatility and open the path towards novel computational structures and approaches, for the traditional Von-Neumann architectures and beyond. These promising characteristics, coupled with the ever-increasing limitations faced by traditional CMOS-based storage and computational structures, have driven the research community towards completely revisiting the existing computing and storage paradigms, now focusing on providing hardware solutions for in-memory and neuromorphic computing. This has resulted in an intensified research activity in the device physics, striving to achieve circuit-worth devices, reliable compact models and novel architectures. The purpose of this paper is to provide a comprehensive overview of the device physics, issues related to its use in electronic circuits, methodologies for their compact modelling and simulations, and their integration in storage and computational structures.

The development of non-conventional Von-Neumann architectures becomes essential for breakthrough computing in Internet of Things (IoT) devices. The main objective for IoT application is to lower as much as possible the power consumption to promote autonomy. The key to solve this challenge is to reduce the data transfer between memory and computing unit. As emerging non-volatile memories and especially resistive switching technologies (ReRAM) can today be co-integrated with CMOS on hybrid process, we propose in this paper to develop bitwise logic operations inside and close to the memory array. Using two transistors - one ReRAM (2T1R) memory cell architecture with differential approach to enhanced read reliability, we can perform logic operations without impacting the global memory architecture. Thanks to parallel data sensing, the structure enables fast computation of any bitwise logic operations (ID, AND, OR, XOR in their natural or complementary form) with high reliability, promoting the computing in memory (CiM) concept.

The last 10 years have seen the rise of new NVM technologies as alternative solutions to Flash technology, which is facing downsizing issues. Apart from offering higher performance than the state of the art of Flash, one of their key features is lower power consumption, which makes them even more suitable for the IoT era. But one of the other main concerns regarding IoT is data security, which is yet to be evaluated for emerging NVM. Our previous work aimed at putting under test the integrity of HfO2based resistive RAM (OxRAM cells). Bit-set occurrences were found after thermal laser attacks. This present work investigates the difference in behaviour when a selector is added to the resistive element, thanks to attack on different stacks. The results obtained give interesting tracks for the design of secure OxRAM-based ICs. It also studies the kinetic role of temperature through heating experiments.

With the introduction of the Internet of Things (IoT), power consumption became a major design issue in modern system-on-chips. In advanced technologies, leakage power has become a dominant component, especially during sleep periods. Leakage mainly comes from volatile memory elements, e.g., flip-flops that cannot be power-gated in order to retain their states. Non-Volatile Flip-Flop (NVFF) using emerging memory technologies, such as Resistive Random Access Memories (RRAM), are popular solutions to address this issue. In NVFF design, the resistance values of the memory element have a direct impact on the area and energy overhead of the structure. In this paper, we present a design methodology for area and energy efficient RRAM-based NVFF. By characterizing the optimal lower bound of the RRAM resistance ratio required for properly restoring the FF, the store and restore operations can be performed using optimal programming circuit area and energy. Four Transmission-Gate (TG) NVFF topologies implemented in 180nm CMOS technology were analyzed using the proposed methodology. The presented methodology shows that differential NVFF provides minimum restore resistance ratio down to 1.02 considering CMOS and RRAM variability. This enables improvements in terms of store energy (34%) and area overhead (40%) compared to reported state-of-the-art NV-TGFFs design approaches.

Recent announcement of 16Gbits Resistive memory from Sony shows the trend to quickly adopt resistive memories as an alternative to DRAM. However, using ReRAM for embedded computing is still a futuristic goal. This paper approaches two applications based on ReRAM-devices for gaining area, performance or power consumption. The first application is FPGA, one of the first architecture that can benefit the most from ReRAM integration to reduce footprint and save energy. The second application relates to ultra-low-power systems and the way to obtain an instantaneous “freeze” mode in devices for Internet of Things.

This paper introduces a new way of monitoring critical parameters directly inside circuits. It describes a flow able to transform a circuit into a test vehicle: the concept is called topological exchange. The principle is to remap existing standard cells to create monitoring functions. The flow is detailed through a specific example of oxide thickness monitoring and the method is validated with post-layout simulations.

This paper presents a direct way to measure the electrical value of capacitors embedded in a circuit using a ring-oscillator. A calibration system ensures robustness towards temperature, power supply and process variations. The measurement is largely automated to minimize the use of external instrumentation and to speed-up the measurement process while giving a digital signature of the capacitor value. Design-Of-Experiment (DOE) methodology has been conducted in order to validate the ability of the system to measure robustly a large range of small capacitors.

At most advanced technology nodes, Field Programmable Gate Arrays (FPGA) present great advantages compared to more conventional processor architectures; their natural regularity, modularity and inherent reliability due to duplicated identical tiles provide a solution to overcome new technologies with increasing variability. However, FPGA market is still limited by power efficiency issue, due to two coordinated factors like interconnection-dominated design and large usage of memories, computation being performed thanks to Look-Up-Table (LUT). In this paper, we propose a solution to improve the performance and reduce the power consumption of LUT in FPGA using CBRAM-based structures. Our proposed design shows significant improvement compared to the traditional SRAM-based FPGA in: critical delay is reduced by ~23% due to compact structure (1T-2R) and power gain by reduction in static power consumption by ~18%.

This paper presents a built-in tuning technique in radiofrequency receivers using on-chip polyphase filters. Auto-calibration of the filter resistance values, based on Design-Of-Experiment (DOE) methodology, is proposed. This approach investigates process and temperature monitoring of the frequency band, the image-rejection-ratio (IRR) and the I/Q-accuracy resulting in robust and low-cost solutions.

Analog circuit designs are often biased to work in sub-threshold mode for low power constraints and for better gate-source voltage matching performances. Depending on process, hump effect may change MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. Actually, even without body effect, hump mainly degrades MOS matching performances in the sub-threshold area with significant temperature dependence. Thus, in order to accurately simulate bandgap performances, modeling of hump effect has to be considered.

The constant evolution of technologies involves a large amount of problems during and after Flash memory manufacturing. In this context, manufacturers must develop methods and design solutions to improve reliability especially for automotive applications. For this purpose, ECC and BISR are probably the most efficient concepts to enhance memory reliability. However, such techniques are limited to correct errors occurring punctually within a word whereas in memories the stress of peripheral circuit can lead to an entire faulty bit or word line. This phenomenon is referred as Clustering Effect. This work proposes an on-line testing structure for clustering effects according to the word line plan. This test structure allows achieving a test time acceptable and is shown as low cost in term of surface overhead (3 HV transistors, 1 XOR, 1 MUX and 1 DFF). Adding our solution to recent ECC and BISR techniques, spatial or automotive applications could be easily targeted.

Emerging concepts of non-volatile memories are more and more investigated to replace conventional charge storage-based devices like EEPROM or Flash. One of these promising memory concepts is called Resistive Switching Memory (ReRAM). Such memory is based on a switching mechanism controlled in current and/or voltage, between two distinct resistive states depending upon the material nature integrated in memory element. To lead such memory concept to a memory circuit or even, to a product, a big effort has to be done to forecast tools necessary to design and test this emerging memory. In this paper, a particular technology of ReRAM memories is introduced. First, an electrical model (ELDO-like) of a MIM-based (Metal/Insulator/Metal) ReRAM memory element is presented. Then, this model is used for the robustness assessment of ReRAM memory element in presence of actual defects inherent to CMOS process steps. Based on this electrical model, a big hurdle has been broken between material physics, design and test. Thus, new methods and solutions could be developed in the field of design and test for ReRAM memories.

The low-power consumption, the high integration density and the flexibility make Flash memories popular for portable electronic devices. Unfortunately, the aggressive evolution of technologies and the particular Flash memory process induce more and more complex faults in such memories. This paper addresses the main detractor of the Flash testing time, namely the test of Address decoder Faults (AFs). The first part of the paper is devoted to an analysis of the well known 5-steps Flash test flow also called 5-steps basic sequence. Based on this analysis, the critical points of such test strategy are shown from fault coverage and test time points of view. Next, these critical points are identified and associated to a particular pattern, namely the Diagonal `0' pattern. In the fourth part of the paper, the functional fault models (AFs) given by [1] are transposed to a structural level (St_AFs). This structural transposition opens the way to new ad-hoc test solutions. According to this transposition, a structural-based method is proposed to avoid the Diagonal `0' pattern in a global 5-steps basic sequence. This method states on a monitoring structure that performs the detection of St_AFs. Finally, the fault coverage of our solution is evaluated and compared to the Diagonal `0' pattern. Our solution achieves a 100% coverage rate of AFs whatever the memory size whereas the Diagonal `0' pattern has a fault coverage that never reaches 100% and decreases with the memory size.

The objective of this paper is to present a flash cell model for static and transient simulations. As a core element of this model, a Philips MOS model (MM11) model has been used coupled with the charge neutrality expression in the structure. The charge neutrality, including the charge trapped in the floating gate, is applied to determine the potential of the floating gate. From the floating gate potential, related to the terminal voltages, the drain current and the different charges present in the cell structure are calculated with the MM11 formulation. This pragmatic model takes into account the different injection mechanism (CHE, CHISEL and FN). Moreover, the characterization procedure developed under ICCAP to extract the MM11 model card as well as the tunnel current parameters is presented. This model has been successfully implemented in ELDO

The embedded DRAM (eDRAM) is more and more used in system-on-chip (SOC). It is challenging to integrate the DRAM capacitor process into a logic process to get satisfactory yields. The specific process of DRAM capacitor and the low capacitance value (/spl sim/30 fF) of this device induce problems of process monitoring and failure analysis. We propose a new test structure to measure the capacitance value of each DRAM cell capacitor in a DRAM array. This concept has been validated by simulation on a 0.18 /spl mu/m eDRAM technology.

Parametric failures in CMOS IC nanoelectronics, leads to strong detection problem. In order to develop new defect oriented test methods, it is of prime importance to study the behavior of the transistor affected by those kind of failures. In this paper, we present a new electrical transistor model, which allows to study the impact of gate oxide thickness drop. It is shown that electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.

The objective of this paper is to present an automated geometric defect diagnosis methodology for EEPROM cell (AGDE). This method focuses on speeding up the diagnosis process of geometric defects. It is based on a mathematical model generated with a "design of simulation" (DOS) technique. The DOS technique takes as input, simulations results of a floating gate transistor with different given geometries and produces, as output, a polynomial equation of the threshold voltage in function of the cell's geometric parameters. The diagnosis process is realized by comparing the measured threshold voltages of an EEPROM cell with the dynamically computed ones. From this comparison, the potentially defective geometric parameters are automatically extracted.

Proposes a new and original FPGA architecture with testability facilities. It is first demonstrated that classical FPGA architectures do not allow one to efficiently implement sequential circuits with a scan chain. It is consequently proposed to modify the architecture of classical FPGAs in order to create an implicit-scan chain into the FPGA itself called implicit scan FPGA (IS-FPGA). Using this new FPGA architecture, any sequential circuit implemented into the FPGA is 'implicitly scanned'. An original and optimal implementation of the proposed architecture is given with minimum area overhead and absolutely no delay impact. Additionally the technique is transparent for the user as well as for the FPGA mapping tools. Finally, it is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits.

The objective of this paper is to generate an Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault." Then, it is commented that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is also commented that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.

This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA. The proposed approach is applied to the XILINX SPARTAN, 4000 and 3000 families. On these examples of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then for a single logic cell, and finally for the m/spl times/m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configurations for a single logic cell. An approach is then described to define a minimum number of test configurations for a logic cell knowing the test configurations of its logic modules. This approach gives only 4 test configurations for the XILINX Spartan, 5 for the 4000 and 4 for the 3000 while the previous published works concerning Boolean testing of these FPGA families give 8 for the 4000 and 5 for the 3000.

The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. In usual SRAM-based FPGAs, Configurable Interface Modules (CIMs) can be found between the global interconnect and inputs of the logic cells (input CIMs) or between output of the logic cells and the global interconnect (output CIMs). It is demonstrated that an input CIM that connects N/sup in/ segments to a logic cell input requires N/sup in/ test configurations and that an output CIM that connects a logic cell output to N/sup out/ segments requires 2 test configurations. Then, it is proven that a set of K/sup in/ input CIMs can be tested in parallel making the number of required test configurations equal to N/sup in/. In the same way, a set of K/sup out/ output CIMs is shown to require only 2 test configurations if N/sup out/>K/sup out/. Finally, it is shown that the complete mXm array of logic cells with K/sup in/ input CIMs and K/sup out/ output CIMs can be tested with only N/sup in/ test configurations using the XOR tree and shift register structures.

This paper address the problem of testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. The Configurable Interface Modules (CIMs) are assumed to be implemented with FPGA multiplexers but the results can be easily extended to any type of interface module. First, it is demonstrated that an address bit Configurable Interface Multiplexer requires N=2/sup n/ test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable Interface Modules with n address bits is analysed and it is proven that the set of CIMs can be tested in parallel making the number of required test configurations equal to N=2/sup n/. Third, it is shown that the complete circuit, i.e. a m/spl times/m array of sets of k Configurable Interface Multiplexers with n address bits can be tested with only N=2/sup n/ test configurations using the XOR tree and shift register structures.

This paper presents a novel technique for testing Field Programmable Gate Arrays (FPGAs), suitable for use in the case of frequent FPGA reuse and rapid dynamic modifiability of the implemented function.

This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic test configurations to fully test the whole matrix of CLBs. In the proposed test configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of test configurations 8 is fixed and independent of the FPGA size.

This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2/sup N/ memory cells is proposed taking into account the LUT and RAM modes. Concerning the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the march tests. We also propose a unique test configuration called 'pseudo shift register' for mxm arrays of modules. In this configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called 'shifted MATS++' is described. Concerning the LUT mode, we use the concept of non-redundant test that proposes to test in LUT mode the parts of the module not tested in RAM mode. Under this hypothesis, it is demonstrated that the test of a single module as well as the test of an mxm array of modules require only 3 test configurations. Using our solution, the test of a complete array of mxm LUT/RAM modules requires 4 test configurations independently of the size of the array and of the modules.

The test of the Configurable Logic Blocks of RAM based FPGAs under a Stuck-At fault model has been studied. The high cost of changing the configuration, by reprogramming the FPGA during testing, forces a strategy to reduce the number of different configurations used for testing purposes. After finding the optimal solutions for the elementary structures of the Logic block, Multiplexers and Look-Up Tables, the problem of testing interconnected elementary structures is addressed. The method is illustrated using an elementary structure and then applied to a popular FPGA (XILINX 3000 family) where a reduced set of configurations (5) and their corresponding test sequences is found to cover all (100%) the Configurable Logic Block faults modelled.