A new class of CMOS VLSI asynchronous sequential circuits utilizing pass transistors is introduced. This class of self synchronizing circuits eliminates the need for critical race free state assignments. These circuits synchronize the transition path action by forcing the circuit to sequence through proper unstable states.>

A novel design procedure for VLSI asynchronous sequential circuits is presented. It is based on partition algebra and generates circuits that use fewer transistors compared to previous procedures. This design procedure is simple and produces circuits that have very regular structures and are faster compared to the circuits generated by the existing procedures. This is due to the reduced number of transistors in the chain connected to the buffer. The circuits are generated by replication of similar units. This leads to a regular layout, and the small blocks can be optimized for optimum performance. This procedure can be extended to synchronous sequential machine design by replacing the buffer with a D flip-flop.>

The authors1have used a coding theory approach in an attempt to design fault-detecting and fault-tolerant asynchronous sequential machines. While the method appears to be sound from theoretical aspects, actual attempts to implement these design procedures reveal a serious shortcoming which should be made known.

Fail-safe circuits are designed to assume a 1 (1-fail-safe) or a 0 (0-fail-safe) output state upon failure. This correspondence extends fault detection techniques previously presented [1] to include the design of fail-safe asynchronous sequential circuits. Faults causing failures in the internal state logic and the output state logic circuitry are treated. These failures are assumed to be symmetric and the resulting circuit realizations require less hardware than realizations derived from previously presented techniques.

A general design technique for achieving single fault-tolerant asynchronous sequential circuits is described. The design procedures apply over a large range of fault conditions and are extremely easy to use. Generally, less than three times the logic required for a single copy is needed to achieve single fault tolerance. In addition to fault tolerance, real time fault detection is easily achieved and it is immediately known when single fault tolerant capability is exceeded.

A design procedure is presented which allows for detection of faults in asynchronous sequential machines in a real time environment. Faults affecting both the output states and the internal operation of the machine are detected. The class of faults initially considered are single stuck-at-1 and stuck-at-0 faults. However, since the detection system presented is static and continuous, the class of faults detected will be greatly extended to include intermittent and a large number of multiple faults.

A logic designer may inadvertently select the design equations in such a way that stable states other than those of the flow table are formed. During malfunctions, it is possible for the circuit to assume a set of stable states that are not members of the original flow table, causing improper action. In some cases, it is impossible for the circuit to reassume the stable states of the flow table, creating a "critical situation." A safe circuit is one that is free of the critical situation.

Observations are made relative to the choice of state assignments demonstrated in a recent note' on state assignment selection. Counter examples are given to indicate that the problem of selecting state assignments is not solved as the author implies.

Critical race-free internal-state assignments can be found by several methods. Often these methods produce several assignments for the same flow table. New and improved tests are presented that can be used to select that assignment which is most likely to produce a set of simple design equations. These tests are applicable to the next-state equations as well as the output equations. The tests are applicable to circuits that are to be realized with NAND gates or set-reset (SR) flip-flops. Another advantage of these tests is that they allow comparison between state assignments with differing numbers of internal-state variables.

This paper presents a new procedure for constructing nonuniversal shared-row internal state assignments for asynchronous sequential circuits. The method consists basically of establishing an initial code with the minimum number of variables required to distinguish the states. satisfactory assignment is obtained. State variables added in the expansion of an assignment are merely the EXCLUSIVE OR of state variables in the original assignment. This simple construction procedure terminates with a maximum of m+[m/2] state variables for a 2m-row flow table.

Described here is a linear code that has a maximum distance between codewords ofkfor a code of order2^k. Since the minimum-maximum distance iskfor a code of order2^k, a class of minimum-maximum distance codes results. For an(n,k)linear code,k \leq n \leq k + k/2forkeven andk \leq n \leq k + (k - 1)/2forkodd. Maximum-distance codes are found useful in encoding the states of sequential circuits.

Methods already exist for the construction of critical race-free assignments for asynchronous sequential circuits. Some of these methods permit the construction of many assignments for the same flow table. The algorithm presented here consists of two easy to apply tests which select that critical race-free assignment most likely to produce a set of simple next-state equations. The algorithm has been programmed.

One step in the synthesis procedure for realizing an asynchronous sequential switching circuit is the generation of next-state and output state equations from a simplified and coded flow table description of the circuit. The usual approach for determining these equations is to first construct a state table from the coded flow table, and then construct transition and output tables. For large flow tables this can be quite a lengthy procedure. This note describes an algorithm which simplifies the synthesis procedure for normal fundamental-mode circuits by permitting the determination of these equations without explicit construction of the state table, transition table, or output table. The algorithm has been programmed in PL/1.