Abstract The application of Large Language Models (LLMs) in Model-Driven Engineering (MDE) has emerged as a rapidly evolving research area. While existing systematic literature reviews have examined specific technical approaches, a comprehensive mapping of the broader research landscape (e.g., development trends) remains lacking. This study presents a systematic mapping study of LLM applications in MDE, analyzing 86 primary studies collected from five databases, covering publications from 2022 to early 2026. Guided by five research questions, we characterize the field across five dimensions: MDE task distribution and research contribution types, LLM technologies and interaction strategies, artifact representation and processing, validation practices, and publication landscape. Our findings reveal that current LLM4MDE research is heavily concentrated on Model Generation, while tasks such as Model Migration, DSL Engineering, and Metamodeling remain marginal. Most approaches rely on black-box OpenAI models accessed via remote APIs and adapted through prompt engineering, with fine-tuning and retrieval-augmented generation rarely employed. Inputs are predominantly natural-language artifacts, while outputs are model-oriented but usually expressed in lightweight textual formats rather than native MDE exchange formats. Validation is centered on quantitative experimentation, with 42% of studies reporting no baseline and cost efficiency reported in fewer than one quarter of studies. The field has grown rapidly, from one paper in 2022 to 42 in 2025, with research concentrated in Europe and Canada and limited industry involvement. Based on these findings, we identify gaps and opportunities across task coverage, technical configuration, and evaluation practice, offering a knowledge map to guide future work in this cross-disciplinary field.

Decap allocation are the primary methods for addressing the dynamic voltage noise problem of on-chip power networks. When space in the immediate proximity of a hot spot is constrained, simply adding decoupling capacitance without improving the local wiring is ineffective. Based on this key observation we proposed an effecient co-optimization of decap allocation and local wiring enhancement. The method solves a linear program (LP) iteratively and is based on the decap budgeting algorithm [10]. Experimental results on two actual chip designs demonstrate the area and run-time efficiency of the co-optimization algorithm. Moreover, it provides excellent solutions even in cases where decap allocation alone fails to provide a feasible solution.

We propose a novel and efficient incremental analysis technique for 'what-if analysis of on-chip power distribution networks (PDN). Effect of local modifications to a PDN, including local topology changes, can be quickly analyzed without need for very expensive re-analysis of the entire modified network. We borrow ideas from a fictitious domain method that has been successfully used in solving partial differential equations arising from inhomogeneous problems in mechanics. The effect of local wiring modifications in several PDN regions is mimicked by applying fictitious currents at the boundaries of these regions in the original unmodified network. The fictitious currents are calculated from component sub-problems in a low-computation iterative procedure. The practicality of this method for use in what-if analysis is demonstrated with several large power networks from actual industrial designs. It analyzes a modified network with few million changes in a fraction of time it would take for a complete re-analysis.

We propose a novel and efficient charge-based decoupling capacitance budgeting algorithm. Our method uses the macromodeling technique and effective radius of decoupling capacitance to reduce the size of the problem. We formulate the nonlinear optimization into a linear program (LP) by integrating the nodal equations across a time period of interest and through certain approximations. To reduce the error caused by linearization, we do multiple iterations of the linear program. Experimental results demonstrate that, with the proposed algorithm, even very large power networks (eg. 5 million nodes) can be optimized in a couple of hours with 1-2 transient analyses. Comparison of our algorithm with another heuristic method shows area efficiency and run time advantage of our method.

Power-distribution networks of very large-scale integrated (VLSI) chips should be designed carefully to ensure reliable performance. A sound power network requires an adequate number of power-supply input connections (pads and pins). Placing them at the best vantage locations helps to reduce the number of supply connections necessary for obtaining quality power distribution. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power-supply network, subject to constraints on the voltage drops in the network and maximum currents through the pads, pins, and regulators. The problem is modeled as a mixed-integer linear program (MILP) with the help of macromodeling techniques. Two new heuristics, in addition to the commonly used branch-and-bound technique, are proposed to make the problem tractable. The effectiveness of the proposed technique is demonstrated on several real chips and memories used in low-power and high-performance applications.

Power delivery networks of VLSI chips require adequate input supply connections to ensure reliable performance. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power supply network, subject to constraints on the voltage drops in the network and maximum currents through the pads, pins and regulators. The problem is modeled as a mixed integer linear program using macromodeling techniques and several heuristic techniques are proposed to make the problem tractable. The effectiveness of the proposed techniques is demonstrated on several real chips and memories used in low-power and high-performance applications.