Reactualisation de l'article ecrit en 1961, par W.L. Everitt, sur les perspectives d'evolution de la formation des ingenieurs, jusqu'en 2012, aux Etats Unis

The authors investigate a power estimation technique for VLSI that combines the accuracy of simulation-based techniques with the speed of the probabilistic techniques. The resulting method is statistical in nature; it consists of applying randomly generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The authors present the algorithm and experimental results, and discuss the superiority of the approach.>

An alternative technique for power estimation that combines the accuracy of simulation-based techniques with the speed of the probabilistic technique is investigated. The resulting method is statistical in nature; it consists of applying randomly-generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The algorithm and experimental results are presented and the superiority of this approach is discussed.>

iEDISON optimizes the transistor sizes of a circuit so that its performance is least sensitive to manufacturing process fluctuations. iEDISON considers three methods for design optimization, namely, the response surface method, the Taguchi method, and the nonnested experimental design method. These methods use experimental designs and regression models to explore the statistical performance variations. The efficiency of the system is demonstrated by an example on clock-skew minimization.>

A hierarchical parasitic circuit extractor HPEX for Manhattan layouts is described. HPEX can model interconnection lines as distributed lumped circuits directly from a circuit layout by using analytical formulas instead of numerical methods. The difference in feature sizes between mask layouts and actual fabricated conductors is also taken into account by a geometrical preprocessing algorithm based on a novel Y-X scanline method and a simple rectangle data structure. In addition, a simple and accurate node reduction technique based on the concept of Elmore's delay is employed in HPEX to make layout verification simpler. All features mentioned above clearly indicate that HPEX will be a promising tool in verifying VLSI system performance especially when interconnect parasitics associated with VLSI circuits are taken into consideration.

This paper describes the algorithms used in a presimulation phase to partition an MOS digital network into various special subnetworks (or blocks) and to order these subnetworks for processing in a switch-level timing simulator such as MOSTIM [1]. A transistor-level SPICE2-type [3] description of the network is assumed to be provided. The key to the partitioning strategy is to divide the set of enhancement transistors into driver and pass transistors. The driver transistors are then grouped together in a de-connected sense to form multiple-input single-output combinatorial logic blocks, while the pass transistors are grouped together to form pass transistor blocks. A graph algorithm performs the partitioning step in computation time that is linear with the number of enhancement transistors. The partitioning step is an automatic process that is completely transparent to the user. The partitioned blocks are then ordered for simulation such that, whenever possible, a block is scheduled for processing only after all its input waveforms are known. A clear and precise notion of feedback among the various blocks in the partitioned network is introduced, and a distinction is made between feedback among different blocks and feedback internal to a block. It is shown that a good ordering for processing the blocks in a network is possible only in the absence of any form of feedback among the blocks. In case of a partitioned network with feedback, a linear time algorithm is presented that detects the strongly connected blocks, which are then flagged for simulation using special dynamic windowing techniques [4]. The strongly connected components are then topologically ordered for simulation.

A major cost in statistical analysis occurs in repeated system simulation as system parameters are varied. To reduce this cost, the system performances are approximated by regression models in terms of critical system parameters. These models are then used to predict the performance variations and parametric yield. This paper presents a systematic and computationally efficient method for deriving regression models of MOS VLSI circuit performances that can be used to estimate the parametric yield. This method consists of four fundamental steps: simulation point selection, model fitting and validation, model improvement, and parametric yield estimation. An average mean-squared error criterion is used to select an optimal set of points in the design space for circuit simulations, and the adequacy of the fitted regression model is checked rigorously. It will be shown through examples that accurate statistical performance models and parametric yield estimate for MOS VLSI can be derived by using four or five critical device parameters and a small number of circuit simulations.

This paper discusses the algorithms and implementation necessary for computing time domain sensitivities during circuit simulation. The adjoint approach and the direct approach have been studied, and it was concluded that the direct approach is the best for implementation. The direct approach allows the transient sensitivities to be computed concurrently in time with the normal simulation, and it has been demonstrated that accurate sensitivity computations can be obtained, by simply allowing the sensitivity circuits to use the same time steps as the original circuit. This implementation also incorporates the charge based model for the MOSFET's and those sensitivity derivations are shown. It has been found that the responses of the sensitivity circuits can be discontinuous, and that this is due to discontinuities in the derivatives of the charge with respect to voltage. Derivations for various performance function sensitivities in terms of the response sensitivities are also given.

This paper is concerned with the computational problem of maximizing the yield of circuits. A statistical Monte Carlo based approach is taken in order to compute yield estimates directly and to decrease dimensionality dependence. The main contribution of this paper is a yield extrapolation technique which is very effective in maximizing the yield along a search direction. This technique is based upon a quadratic model of the circuit. Statistical yield estimates are computed from the model and correlated sampling is used to extrapolate along the search direction. Two simple methods for determining search directions are discussed and these are used to demonstrate the overall method through several examples.

The efficiency of several variance reduction techniques (in particular, importance sampling, stratified sampling, and control variates) are studied with respect to their application in estimating circuit yields. This study suggests that one essentially has to have a good approximation of the region of acceptability in order to achieve significant variance reduction. Further, all the methods considered are based, either explicitly or implicity, on the use of a model. The control variate method appears to be more practical for implementation in a general purpose statistical circuit analysis program. Stratified sampling is the most simple to implement, but yields only very modest reductions in the variance of the yield estimator. Lastly, importance sampling is very useful when there are few parameters and the yield is very high or very low; however, a good practical technique for its implementation, in general, has not been found.

Several methods have become available recently for the determination of the steady-state response of nonlinear circuits. The Newton algorithm is one of the more successful methods. However, in certain cases, the method fails to converge to a steady-state solution. Some modifications to the Newton method to increase convergence reliability or speed are proposed. The implementation of these modifications is discussed. Several example circuits are given and the results compared. Some guidelines for the use of these modified methods are also given.