Augmented reality (AR), which overlays virtual objects onto real scenes, has large potential to provide learners with a new type of learning material. Although many AR systems have been developed for demonstration, there is a gap between their ideal and practical use. We discuss a concept for augmented instructions that mix AR and traditional printed materials. Improvement of human-computer interface is considered to serve as a bridge for the gap. To investigate on characteristics of augmented instructions and its appropriate interface, we conducted subjective evaluation, comparing 3D presentation systems; a handheld PC and a head-mounted display. The result suggested that a handheld PC was more suitable for a presentation tool of augmented instructions.

In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitance in a wire are included in interconnect delay calculation. Combined with general ASIC design flow, we construct section constraint graph in each routing region and use the graph to guide segment sizing and spacing. By defining a cost function to trade-off between interconnect delay and routing area, we formulate wire sizing and wire spacing problem (WSSP) into a constraint-optimization problem and develop a heuristic algorithm to solve it. The preliminary experiments are promising.

This paper presents a novel algorithm for summing a set of 2's complement numbers in parallel. The 2's complement addition is converted to an equivalent parallel summation of unsigned numbers. The conversion is performed by simply complementing all the sign bits. Only a few constant bits are required for sign correction. This algorithm is suitable for computer-aided design (CAD) of custom VLSI.

This paper presents new algorithms for routing two rows of interchangeable terminals across a 2-layer channel. The number of horizontal tracks required for routing is significantly reduced by simply interchanging terminals in each cell. Savings up to one-third of horizontal tracks or more are achieved by interchanging terminals. The Deutsch Difficult Example is used as a test routing problem. The number of horizontal segments per net is limited to one, no "doglegs." The program is coded in Pascal and implemented on a VAX-11/780 computer.

This paper investigates architectures for digital signal processors (DSP's). Typical DSP's are examined to identify their computation and communication requirements. By decomposing the general filtering function into primitive second-order digital recursive filter (2DRF) modules, an architecture is developed which contains the basic operations of every signal processor. This leads to the design of a novel, programmable arithmetic unit for high speed sum-of-product (SOP) computation which possesses hardware speed and software flexibility. For spectral decomposition of speech, a number of DRF modules must operate simultaneously. A set of MC68000 microcomputers is used to identify the interprocessor communication requirements for modules acting as a digital filter bank (DFB). A versatile bus structure permits the investigation of various data transfer and control strategies for different systems. This leads to the design of a VLSI DFB for real-time speech processing.

This paper presents a novel arithmetic scheme for a high-speed adaptive learning network (ALN) element. An ALN is a self-organizing scheme for implementing the Kolmogorov-Gabor (K-G) polynomial which maps an input vector X into an output scalar Y. In the first layer of an ALN there are n(n-l) / 2 elements. In the next layer the number of elements needed depends upon the number of outputs that are propagated from the first layer. In this paper only the design of a single element is considered. An array of memories (RAMs) and a parallel adder are used to perform multinomial arithmetic for the element. The memory array contains subfunction values which are calculated by an external host computer and downloaded to the memory array. All the memories operate on the input variables concurrently via a common address bus. The subfunction values from the memory array are then summed by a parallel adder to obtain the output of the element. A complete ALN implemented with the proposed ALN elements has advantages in operation speed and less hardware.

Recent developments in integrated circuit technology have made efficient schemes for computer arithmetic possible. This paper discusses a generation-summation scheme for fast multi-operand multiplication. Synthesis of three-operand multipliers utilizing a single type of standard LSI device is also discussed.

This correspondence introduces an extended method of parallel counting which enables small parallel counters to generate larger ones. It is an extension of the Method of Carry Showers by Foster and Stockton to a (u,v)-counter network. A (u,v) counter is a small parallel counter with u inputs and v outputs, u = 2v− 1. It is shown that the counter delay is proportional to the log of the number N of inputs and the total number of elements is approximated by N/(u-v).