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Douglas J. Smith

dblp:08/5773 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware description language		 0.011996
VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C · DAC 1996
Electronic design automation › hardware description language
register-transfer-level modeling		 0.011996
VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C · DAC 1996

Methods — techniques the papers use, named apart from their topics

algorithmic-level modeling · 0.0RTL modeling · 0.0
YearPublicationVenuePosition
1996 VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C
abstract
This tutorial is in two parts.The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their diffrences.The second part contains a worked example of a model that computes the Greatest Common Divisor (GCD) of two numbers.The GCD is modeled at the algorithmic level in VHDL, Verilog and for comparison purposes, C. It is then shown modeled at the RTL in VHDL and Verilog.33rd Design Automation Conference ® Permission to make digital
Douglas J. Smith
 DAC1