Utilizing the nonuniform latencies of SDRAM devices, access reordering mechanisms alter the sequence of main memory access streams to reduce the observed access latency. Using a revised M5 simulator with an accurate SDRAM module, the burst scheduling access reordering mechanism is proposed and compared to conventional in order memory scheduling as well as existing academic and industrial access reordering mechanisms. With burst scheduling, memory accesses to the same rows of the same banks are clustered into bursts to maximize bus utilization of the SDRAM device. Subject to a static threshold, memory reads are allowed to preempt ongoing writes for reduced read latency, while qualified writes are piggybacked at the end of bursts to exploit row locality in writes and prevent write queue saturation. Performance improvements contributed by read preemption and write piggybacking are identified. Simulation results show that burst scheduling reduces the average execution time of selected SPEC CPU2000 benchmarks by 21% over conventional bank in order memory scheduling. Burst scheduling also outperforms Intel's patented out of order memory scheduling and the row hit access reordering mechanism by 11% and 6% respectively

The performance contributions of SDRAM address mapping techniques in the main memory of an embedded system are studied and examined. While spatial locality existing in the access stream increases SDRAM row hit rate, it also increases row conflicts. Mapping of the physical address bits into SDRAM column, row, bank and rank index impacts system performance significantly. A novel address mapping scheme, called bit-reversal, is described and experimentally compared against known methods. The bit-reversal address mapping increases SDRAM row hit rate from 43% to 66% by distributing conflicting memory accesses over independent SDRAM banks. Bit-reversal address mapping reduces the average memory access latency by 26%-29% over other methods, resulting in a 11.7%-13.5% reduction of total execution time. The configuration space of bit-reversal address mapping is explored. Finally, limited studies examining the impact of address mapping techniques in conjunction with SDRAM controller policy and virtual paging illustrate that mapping is better suited to virtual memory free embedded systems than desktop workstations incorporating paging mechanisms.

Memory hierarchy performance, specifically cache memory capacity, is a constraining factor in the performance of modern computers. This paper presents the results of two-level cache memory simulations and examines the impact of exclusive caching on system performance. Exclusive caching enables higher capacity with the same cache area by eliminating redundant copies. The experiments presented compare an exclusive cache hierarchy with an inclusive cache hierarchy utilizing similar L1 and L2 parameters. Experiments indicate that significant performance advantages can be gained for some benchmark through the use of an exclusive organization. The performance differences are illustrated using the L2 cache misses and execution time metrics. The most significant improvement shown is a 16% reduction in execution time, with an average reduction of 8% for the smallest cache configuration tested. With equal size victim buffer and victim cache for exclusive and inclusive cache hierarchies respectively, some benchmarks show increased execution time for exclusive caches because a victim cache can reduce conflict misses significantly while a victim buffer can introduce worst-case penalties. Considering the inconsistent performance improvement, the increased complexity of an exclusive cache hierarchy needs to be justified based upon the specifics of the application and system.