We present a profiling based technique for power estimation. This technique is implemented in the PDSS (Profile Driven Synthesis System) for the synthesis of low power designs. Initially, each module in the module library is characterized for the average switching capacitance per input vector. The input description is simulated using user-specified set of input vectors to collect the profile data for various operators and carriers. The profile data, in conjunction with the pre-characterized module library is used to estimate the total capacitance switched by each of the valid schedules produced by the PDSS scheduler. A valid schedule is one which satisfies other constants such as area and delay. The schedule with the least switching capacitance estimate is further synthesized to the layout level. Results show an average deviation of 12% compared with the actual switching capacitance values at the layout level.

The goal OJ functional validation of a high-level synthesis system is to a$sert, with a reasonable degree of confidence, that the layouta generated by the high-level synthesis system correctly implement the ~pecified behavior.This paper presents a systematic approach to functional validation baaed on the analysis of specification language constructs, de8ign example formation to cover combinations of constructs, ted-bench generation and automated te8t re8u!t comparison.we have 8ucce88.fu![y applied thi8 approach in validating a high-level 8ynthe8i8 8 stem, called 33 DSS, which accepta specifications stated in VI-I L. This effort Te8u[ted in the development of a functional validation suite corssiding of 29 design ezample.s. 1