Designing logic circuits using complementary metal-oxide-semiconductor (CMOS) technology at the nano scale has been faced with various challenges recently. Undesirable leakage currents, the short-effect channel, and high energy dissipation are some of the concerns. Quantum-dot cellular automata (QCA) represent an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard CMOS. The key point of designing arithmetic circuits is based on the structure of a 1-bit full adder. A low-complexity full adder block is beneficial for developing various intricate structures. This paper represents scalable 1-bit QCA full adder structures based on cell interaction. Our proposed full adders encompass preference aspects of QCA design, such as a low number of cells used, low latency, and small area occupation. Also, the proposed structures have been expanded to larger circuits, including a 4-bit ripple carry adder (RCA), a 4-bit ripple borrow subtractor (RBS), an add/sub circuit, and a 2-bit array multiplier. All designs were simulated and verified using QCA Designer-E version 2.2. This tool can estimate the energy dissipation as well as evaluate the performance of the circuits. Simulation results showed that the proposed designs are efficient in complexity, area, latency, cost, and energy dissipation.

Implementing wireline receivers with a front-end analog-to-digital converter (ADC) allows for complex, flexible, and robust signal processing algorithms in the digital domain, as well as easy implementation of advanced modulation schemes beyond binary PAM2. However, the power consumption of the ADC and ensuing digital equalization is a key issue for such receivers in high-speed applications. Embedding analog equalization inside the ADC architecture allows for both a lower ADC resolution and a reduced-complexity digital equalizer, resulting in a more power-efficient receiver. This article presents a 6-bit 1.5-GS/s time-interleaved successive approximation register (SAR) ADC with low-overhead two-tap embedded decision-feedback equalizer (DFE). A smart speculative DFE is proposed to reduce additional conversion cycles required for the equalization realization in the ADC. Moreover, DFE functions are efficiently embedded in the capacitive digital-to-analog converter (DAC) references. The prototype ADC with two-tap DFE is implemented in a 130-nm CMOS process and achieves a 5.24-bit peak effective number of bits and 0.59-pJ/conversion-step figure-of-merit (FOM) at a 1.5-GS/s sampling rate while consuming 34.1 mW and occupying a core area of 0.32 mm2. The effectiveness of the embedded DFE in timing margin improvement is verified for 1.5-Gb/s operation over high-loss FR4 channels at a bit error rate (BER) of 10-9.

Object recognition in the visual cortex of mammals and humans has inspired many computational object recognition models. Hierarchical model and X (HMAX) is a well‐known biologically motivated object recognition model with scale and position tolerance and high accuracy. Due to the computational intensive nature, hardware implementation with massive parallel processing is suggested for real‐time applications. However, it is important to explore algorithmic trade‐offs when mapping an algorithm to are configurable hardware. A direct conversion of the software implementation of an algorithm generally results inefficient hardware resource usage. In this study, the authors propose a novel modification into the HMAX model which makes it suitable for hardware implementation. More precisely, to reduce the number of memory blocks and multipliers of the S2 layer of HMAX produces, they replace the first norm by the second norm, which critically affects the silicon area in an application‐specific integrated circuit implementation or the required resources in field‐programmable gate array (FPGA). To evaluate the proposed model, they implement a pipelined version of the revised model on a mid‐range commercial Xilinx FPGA, i.e. XC6VLX240T platform from a Virtex 6 family of Xilinx using ISE. Compared to the recent hardware implementation of HMAX, the proposed model offers 83% resource degradation in DSP48 slices and 3% in memory blocks.

A fractional multiplying delay-locked loop (FMDLL) for high speed on-chip clock generation applications is presented. The proposed DLL architecture overcomes some drawbacks of phase-locked loops (PLLs) such as jitter accumulation and stability while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier.The output frequency range can be tuned from 1GHz to 2.5GHz with selectable multiplication ratios of M + 0.05 x K where 1 ≤ K ≤ 19. To generate some finer ratios, K could be changed between two consecutive integer numbers. In this situation, a digital delta-sigma modulator could be used to suppress the spurs existing in the output spectrum.