FinFET technology has become an attractive candidate for high-performance and power-efficient applications. However, its susceptibility to defects increases due to the complexity of the process fabrications and smaller feature sizes. This article proposes compact and low-cost analytical models to evaluate the delay increase in FinFET-based circuits due to resistive open defects. The models rely on electrical simulations to precharacterize the circuit library. Analytical expressions are developed for the three types of resistive opens that may occur in FinFET-based logic cells using multifin and multifinger structures. These types of resistive opens include: a resistive open at the drain or source of the transistors (RODS), a resistive open affecting the gate of a single transistor, and a resistive open affecting the gates of both nMOS and pMOS transistors. Compact analytical models are also developed to evaluate the delay increase due to the resistive open defects under process variations. Independent and correlated process variations are taken into account. The analytical models have been validated against SPICE electrical simulations. The proposed analytical models can be used to evaluate the detectability of resistive open defects, significantly reducing the cost of dealing with different defect sizes. Potential applications of the developed analytical models are delineated. This work allows us to have higher quality and reliable electronic products.

This article proposes an electrical analysis of a new defect mechanism, to be named as b-open defect, which may occur in nanometer technologies due to the use of the Self-Aligned Double Patterning (SADP) technique. In metal lines making use of the SADP technique, a single dust particle may cause the simultaneous occurrence of a bridge defect and an open defect. When the two defects impact the same gates, the electrical effects of the bridge and the open combine and exhibit a new specific electrical behavior; we call this new defect behavior a b-open. As a consequence, existing test generation methodologies may miss defect detection. The electrical behavior of the b-open defect is first analyzed graphically and then validated through extensive SPICE simulations. The test pattern conditions to detect the b-open defect are finally determined, and it is shown that the b-open defect requires specific test generation.

In this paper, we analyze the electrical behavior of a new type of technological defect appearing in the most recent technological process achieving extremely high interconnection density by using the Self-Aligned Double Patterning technique (SADP). This totally new defect mechanism, which could not appear in conventional CMOS technologies, is structurally dependent of the SADP technique and can be considered as a simultaneous combination of Bridge and Open: we consequently named it B-open. The electrical behavior of the B-Open defect is analyzed and shown that the defect exhibits some classical electrical characteristics of Bridge defect and Open defect but also an unprecedented electrical mixed behavior of both defects.

FinFET technology is an attractive candidate for high-performance and power-efficient application and is currently used for several electronic products. FinFET technology incorporates new technologies in the manufacturing processes that may generate new defect topologies which need to be considered during test generation. This paper analyzes the electrical behavior of full open gate defects, i.e., a transistor gate with infinite resistance. It is shown that classical models, called single open (SO) and interconnect open (IO), that have been proposed in the past for CMOS technology are not sufficient in FinFET technology. The modern FinFET-based logic cells using multifin and multifinger design techniques give rise to new specific defect topologies called “subset full open gate defect.” The static and dynamic electrical behaviors of the two new topologies, subset SO (SOsub) and subset IO (IOsub), are analyzed, and the detectability of the defect in the context of Boolean testing and delay testing is derived. The detectability is analyzed taking into account process variation, temperature, and power supply control.

This paper presents a comprehensive study towards the identification and quantification of the detectability improvement of resistive open and short defects, brought by specific supply voltage and body biasing conditions applied during manufacturing test. The study is conducted using a didactic circuit implemented in 28nm UTBB FDSOI-RVT (Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator, Regular VT) technology in the context of delay-based test. Electrical simulation results are analyzed in order to both highlight the optimal test conditions overall and evaluate the individual improvement in defect detection brought by each factor (supply voltage and body biasing conditions), for different resistive defect types.

In this paper we propose a methodology for reliability evaluation, failure prediction, and failure mitigation of a STT-MRAM memory under different supply voltage conditions (i.e., DVS scenarios). The methodology is based on the design of read/write failure predictor registers which are able to predict the memory failure probability for a given DVS scenario. The predicted results are used to re-tune the supply voltage such that the memory reliability is assured.

FinFET technology has become the most promising alternative to continue CMOS scaling. However, Finfet design makes use of complex interconnect structures (e.g middle-of-line -MOL- interconnections), and multi-fin and multi-finger devices, which pose a challenge to test open defects. In this paper, open defects at gate locations in FinFET based cells are investigated. The parasitic capacitances of the cells are extracted using Raphael 3D Field Solver. The logic and dynamic behavior of the opens defects is analyzed, and possible defective topologies are defined. Some open locations present behaviors similar to those presented in planar CMOS based circuits. However, most of the open locations present new subtle behaviors. The use of multi-fin and multi-finger devices makes the opens more difficult to detect than in planar CMOS technology and non-detectable opens may pose reliability issues. Hence, a good understanding of the defect behavior is needed in order to develop new test strategies for FinFET based logic circuits to have circuits with higher quality.

Interconnect opens are a major class of defects found in today's nanometer technologies. These defects present subtle behavior that could lead to test escapes and hence compromise test quality. Furthermore, they could become a reliability risk. Low-voltage testing has been suggested as a static test to improve the defect coverage of interconnect opens. In nanometer technologies, process variability is predominant and considering only the nominal value of parameters is not realistic. Hence, process variations should be considered to analyze the behavior of interconnect opens. In this brief, the detection capabilities of low-voltage testing for interconnect opens considering process variations is investigated. A statistical model is used for the interconnect open defect. Correlation between parameters of the affected gates and spatial correlation of the parameters for those gates tied to the defective floating node have been considered. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS85 benchmark circuits. Based on these results, it is suggested to use low VDD in conjunction with favorable logic conditions at the coupling lines to enhance the defect coverage of interconnect opens leading to better test quality and higher product reliability.

One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. In this paper, we estimate the STT-MRAM cell reliability under fabrication- and aging-induced process variability, by evaluating its failure probability. We analyze the effect of control voltage tuning on the fresh and aged cell failure probabilities and, as a result, we propose a power- and aging-aware circuit level variability mitigation technique based on control voltage tuning. We observed that increasing the values of control voltages, the cell failure probability is reduced at different extends (according to the control voltage under variation), but also that the power consumption is increased. As a result, we have identified the control voltage with the highest impact on the fresh cell reliability, and on the endurance of the cell under study. Subsequently, by performing a power/reliability trade-off analysis, the appropriate value of this control voltage is determined.

This paper discusses new implementations of the predictive alternate test strategy that exploit model redundancy in order to improve test confidence. The key idea is to build during the training phase, not only one regression model for each specification as in the classical implementation, but several regression models. This redundancy is then used during the testing phase to identify suspect predictions and remove the corresponding devices from the alternate test flow. In this paper, we explore various options for implementing model redundancy, based on the use of different indirect measurement combinations and/or different partitions of the training set. The proposed implementations are evaluated on a real case study for which we have production test data from 10,000 devices.

In the context of mission-critical, safety-critical, and remote-controlled applications, it is required to equip systems with self-adapting capabilities. Adaptation is required in post-manufacturing to correct yield loss and achieve zero defective parts-per-million as well as during normal operation to account for different application scenarios and for varying environmental conditions. A self-adaptive system must be capable of providing the required high performances after manufacturing and throughout its normal operation regardless the application scenario wherein it is deployed and despite the varying environmental conditions. In this paper, we describe a generic post-manufacturing self-adaptation technique for RF circuits as well as concurrent self-adaptation techniques for a safety-critical medical sensor for glaucoma diagnosis and for a NFC system which is very sensitive to the environment in which it operates.

IR-drop effects are increasingly relevant in context of both design and test. We introduce the event-driven simulator MIRID that calculates the impact of IR-drop to the circuit timing. MIRID performs the simulation on two abstraction levels: timing effects in the gate-level net-list, current and voltage waveform propagation in the electrical model of the power-distribution network (PDN). Switching events at the logic gates are forwarded to the electrical model, where induced currents and their impact on the neighboring PDN nodes are computed. From this information, values of voltages at the Vdd and ground terminals of logic gates are determined, which in turn are used to calculate accurate switching delays of the gates. MIRID supports a generic interface to electrical models, allowing for a seamless integration of arbitrary models of PDN and gate timing. We report experiments based on a simple PDN model that was introduced previously and incorporates a pre-characterized library. The simulation accuracy is validated by matching the results from MIRID and SPICE.

This work investigates new implementations of the predictive alternate test strategy that exploit model redundancy in order to improve test confidence. The key idea is to build during the training phase, not only one regression model for each specification as in the classical implementation, but several regression models. We explore various options for implementing model redundancy, based on the use of different indirect measurement combinations and/or different partitions of the training set.

This paper presents an alternate test implementation based on model redundancy that permits to achieve lower prediction errors than a classical implementation, even if training is performed over a small set of devices. The idea is to build different regression models for each specification during the training phase, and then to verify prediction consistency between the different models during the production testing phase. In case of divergent predictions, the devices are removed from the alternate test tier and directed to a second tier where further testing may apply. The approach is illustrated on a real case study that employs production test data from an RF power amplifier. Results show that, on the contrary to the classical implementation where prediction accuracy degrades when reducing the training set size, the proposed approach permits to preserve prediction accuracy independently of the training set size, while only a very small number of devices are directed to the second tier of the test flow.

In this paper, we investigate an alternate test strategy for RF integrated circuits based on DC measurements. A methodology to select the appropriate DC parameters is presented, that allows precise estimation of the DUT performances while minimizing the number of measurements to be carried out. The method is demonstrated both on simulation test data from a Low-Noise Amplifier (LNA) and production test data from a Power Amplifier (PA). Results indicate that good prediction of the RF performances can be achieved using only a reduced number of DC measurements.

Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM)defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin(DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise.

Parasitic node capacitance and faulty node voltage of a defective node can induce serious parasitic effects on the electrical behavior of SRAMs. This paper evaluates the impact of parasitic memory effect on the detection of single-cell faults in SRAMs. It demonstrates that detection is significantly influenced by parasitic node components; something that is often not accounted for during memory testing. Finally, it shows the impact of parasitic node components on all possible opens in the SRAM memory cell array, using node voltages from GND to VDD.

CMOS IC scaling has provided significant improvements in electronic circuit performance. Advances in test methodologies to deal with new failure mechanisms and nanometer issues are required. Interconnect opens are an important defect mechanism that requires detailed knowledge of its physical properties. In nanometer process, variability is predominant and considering only nominal value of parameters is not realistic. In this work, a model for computing a realistic coverage of via open defect that takes into account the process variability is proposed. Correlation between parameters of the affected gates is considered. Furthermore, spatial correlation of the parameters for those gates tied to the defective floating node can also influence the detectability of the defect. The proposed methodology is implemented in a software tool to determine the probability of detection of via opens for some ISCAS benchmark circuits. The proposed detection probability evaluation together with a test methodology to generate favorable logic conditions at the coupling lines can allow a better test quality leading to higher product reliability.

This paper analyzes the impact of simultaneous switching noise (SSN) on the timing behavior of CMOS digital blocks. The concept of instantaneous transfer function is introduced to interpret noisy signals and perform timing measurements on such signals. It is shown that the average swing during switching is the key parameter to predict the noise impact on the delay of a logic path, whereas the peak of noise is not relevant. The influence of structural parameters such as the block topology is evaluated, and the unpredictable aspect of SSN impact on path delay is highlighted.

In this paper a new electrical model is proposed to be used in fault size based fault simulation of crosstalk aggravated resistive short defects. The electrical behavior of the defect is first described and analyzed in details. Then an electrical model is proposed allowing to efficiently compute the critical resistance determining the range of detectable short resistance. The model is validated by comparison with SPICE simulations.

A high-performance resistive bridging fault simulator SUPERB (Simulator Utilizing Parallel Evaluation of Resistive Bridges) is proposed. It is based on fault sectioning in combination with parallel-pattern or parallel-fault multiple-stuck-at simulation. It outperforms a conventional interval-based resistive bridging fault simulator by three orders of magnitude while delivering identical results. Further competing tools are outperformed by several orders of magnitude. Industrial-size circuits, including a multi-million-gates design, could be simulated with runtimes within an order of magnitude of the runtimes for pattern-parallel stuck-at fault simulation.

We present a simulator which determines the coverage of small-delay faults, i.e., delay faults with a size below one clock cycle, caused by resistive-open defects. These defects are likely to escape detection by stuck-at or transition fault patterns. For the first time, we couple the calculation of the critical size of a small-delay fault with the computation of the resistance range of the corresponding resistive-open defect for which this size is exceeded. By doing so, we are able to extend probabilistic fault coverage metrics initially developed for static resistive bridging faults to small-delay defects.

Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the variations of power/ground lines at the interface between noncoherent logic blocks in order to warn that a logic error is likely to occur. This information can then be used for any scheme that takes corrective actions.

Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, particularly of resistive short defects. Using a probabilistic model of two-line nonfeedback short defects, we quantify the coverage impact of low-voltage and low-temperature testing for different voltages and temperatures. Effects of statistical process variations are not considered in the model. When quantifying the coverage increase, we differentiate between defects missed by the test set at nominal conditions and undetectable defects (flaws) detected at non nominal conditions. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by low-voltage testing and quantify the resulting coverage loss. Experimental results suggest that test quality is improved even if no cost increase is allowed. If multiple test applications are acceptable, a combination of low voltage and low temperature turns out to provide the best coverage of both hard defects and flaws.

This paper analyzes the logic errors in digital circuits due to the presence of simultaneous switching noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called 'minimum switch condition' is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called 'signal coherence condition' is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunction. DFT and ATPG recommendations are derived from this analysis.

A high-performance resistive bridging fault simulator SUPERB (Simulator Utilizing Parallel Evaluation of Resis- tive Bridges) is proposed. It is based on fault sectioning in combination with parallel-pattern or parallel-fault multiple- stuck-at simulation. It outperforms a conventional interval- based resistive bridging fault simulator by 60X to 120X while delivering identical results. Further competing tools are out- performed by several orders of magnitude.

System-in-package (SiP) has recently become a significant technology in the semiconductor industry, offering to the consumer applications many new product features without increasing the overall form factor. In this talk, the basic SiP concepts are first discussed, showing difference between SiP and SoC, illustrated by some examples, drawn from real-life cases. The specific challenges are considered from the testing point of view, focussing on the assembled yield and defect level for the packaged SiP. Various bare-die test techniques to find known-good-dies are described including their limitations, followed by two techniques to test the SiP at the system level: functional system test and embedded component test. A brief discussion on future SiP design and test challenges concludes the presentation.

In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this technique called "analogue network of converters " (ANC) requires an extremely simple additional circuitry and interconnect.

This paper addresses the efficiency of IDDQand more specifically Delta- IDDQtesting when using a realistic short defect model that properly considers the relation between the resistance of the short and its detectability. The results clearly show that the Delta-IDDQapproach covers a large number of resistive shorts missed by conventional logic testing, requiring only a relatively small vector set. In addition a significant number of defects which are proven to be undetectable by logic testing but may deteriorate and result in reliability failures are detected. The Delta- IDDQthreshold and thus the equipment sensitivity is shown to be critical for the test quality. Furthermore, the validity of the traditional IDDQfault models when considering resistive short defects is found to be limited. For instance, the use of the fault-free next-state function for sequential IDDQfault simulation is shown to result in a wrong classification of some resistive short defects. This is the first systematic study of IDDQtesting of resistive short defects. The impact of the threshold on the defect coverage is quantified for the first time. Although the simulation results are based upon a 0.35mum technology, the results and methodology can be transferred to state-of-the-art and NanoTechnologies

This paper analyzes the electrical behaviour of resistive opens as a function of their unpredictable resistance. It is demonstrated that the electrical behaviour depends on the value of the open resistance. It is also shown that detection of the open by a given vector Tirecursively depends on all the vectors that have been applied to the circuit before Ti. An electrical analysis of this recursive effect is presented and a specific ATPG strategy is proposed

In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this technique called "analogue network of converters" (ANC) requires an extremely simple additional circuitry and interconnect

In this work a strategy for testing analog networks, known as transient response analysis method, is applied to test the configurable analog blocks (CABs) of field programmable analog arrays (FPAAs). In this method the circuit under test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks to known input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between fault-free and faulty CABs. Different functions available in the component programming library are studied and a choice is made in order to obtain the best results in terms of sensitivity and test coverage. A functional fault model based on high-level parameters of the transfer function of the programmed blocks is adopted and the relationship between these parameters and CAB component deviations is investigated, therefore allowing to estimate the fault coverage and test application time of the proposed functional test method

The authors present a simulator for resistive-bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look up, thus, exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; interaction of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive-bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed, and quantitative results with respect to all these definitions are given for the first time.

The test of field programmable analog arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an oscillation-based test strategy.

We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) and a technology-specific part. The first model is based on Shockley equations and is valid for conventional but not deep submicron CMOS. The second model is obtained by fitting SPICE data. The third resistive bridging fault model uses Berkeley predictive technology model and BSIM4; it is valid for CMOS technologies with feature sizes of 90nm and below, accurately describing non-trivial electrical behavior in that technologies. Experimental results for ISCAS circuits show that the test patterns obtained for the Shockley model are still valid for the fitted model, but lead to coverage loss under the predictive model.

The effect of the parasitic values on the ground bounce voltage and on the delay is investigated. Also the effect of ground bounce on the delay in depth paths is analyzed. A ground bounce attenuation proposal is investigated. This can be done using a circuitry to generate ground bounce before the activation of the main circuit. The impact on the circuit delay is observed.

An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced so far, it can handle arbitrary non-feedback bridges between two nodes, including ones detectable at higher bridge resistance and undetectable at lower resistance, and faults requiring more than one vector for detection.

In this paper, we propose a technique for an exhaustive testing of all the delay faults in the logic architecture of symmetrical FPGAs, in a Manufacturing-Oriented Test (MOT) context. Previous techniques, concerning the test of delay faults in an FPGA, have mainly focused on delay faults on interconnexions. Our technique enables the detection of delay faults in the logic architecture and can be viewed as a complementary approach to the previous ones. The method uses the reconfiguration property of the FPGA to make easier the test of delay faults. The configuration scheme consists in chaining the logic cells or the Look-Up Tables (LUTs) in a specific way. The chain connects each LUT output to one input of the next LUT. We demonstrate that the test of all the delay faults can be done with only two configurations and a reduced test sequence.

The problem of testing the configurable analog blocks (CABs) of field programmable analog arrays (FPAAs) is addressed in This work. The considered fault model comprises deviations in the nominal values of CAB programmable capacitors, deviations in the programmable gains of CAB input amplifiers and stuck-on/stuck-open faults in CAB switches. The problem of test stimuli generation is solved, in a first approach, by using the oscillation test strategy (OTS), which is associated to a test response analysis external to the device under test. In a second approach, a built-in self-test (BIST) scheme is proposed by associating to the OTS an output response analyzer (ORA) built using the internal FPAA resources. Both approaches are validated using the ispPAC10 FPAA from the Lattice Semiconductor Corporation. In the paper, the approaches are compared in terms of fault coverage, test application time and required external hardware resources for testing. Experimental results show that a good compromise of these aspects can be found by taking the best of each approach.

The use of the oscillation test strategy to test configurable analog blocks of field programmable analog arrays (FPAAs) has been proposed previously, solving the complex problem of test stimuli generation. An improvement to that technique is presented in this paper, using the resources of the FPAA to build an output response analyzer. This new approach offers a full built-in self-test scheme with no area overhead and requiring a low cost automatic test equipment. Experiments show the efficiency of the approach in detecting parametric faults of the tested components.

Test application at reduced power supply voltage (or VLV testing) is a cost-effective way to increase the defect coverage of a test set. Resistive short defects are a major contributor to this coverage increase. Using a probabilistic model of these defects, we quantify the coverage impact of VLV testing for different voltages. When considering the coverage increase, we differentiate between defects missed by the test set at nominal voltage and undetectable defects (flaws) detected by VLV testing. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by VLV testing and quantify the resulting coverage loss. We report the numbers on the increased defect coverage, flaw coverage, and coverage loss for ISCAS circuits.

An application-dependent test strategy to be used by an FPGA user is presented which requires only 3 test configurations. In this specific strategy, the interconnect is first tested by modifying the logic block configuration and preserving the interconnect configuration. Then, the used logic blocks are fully tested by modifying the interconnect configuration. Results for some benchmark applications mapped into the Xilinx FPGAs are also provided.

Gate Oxide Short defects are becoming predominant as technology is scaling down. Boolean and I/sub DDQ/ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because art accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive characteristic of the GOS as a function of the GOS resistance and location.

Detecting delay faults in SRAM-FPGAs can be done resorting to BIST. In this context, the objective of this paper is to analyse the timing behaviour of look-up tables (LUT) contained in FPGAs in both fault-free and delay faulty cases. We first show that the propagation delay of a LUT depends both on the transition pattern applied to its inputs and on the function implemented in it. This significant result questions the use of the basic assumption - the propagation delay of a LUT is independent of the function realized by it $considered in a number of recent papers. We next demonstrate that i) some physical defects in a LUT can change its propagation delay and ii) the delay due to a timing defect within the LUT varies depending on the location of the defect. We therefore conclude that unlike what is often done in existing FPGA BIST techniques, LUTs cannot be considered as programmable black boxes during test and testing their structure, either fully or partially, is needed to guarantee complete coverage of delay faults in the FPGA.

International audience

We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; reciprocal action of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time.

This paper validates a linear histogram BIST scheme for ADC testing. This scheme uses a time decomposition technique in order to minimize the required hardware circuitry. A practical implementation is described and the structure together with the operating mode of the different modules are detailed. Through this practical implementation, the performances and limitations of the proposed scheme are evaluated both in terms of additional circuitry and test time.

Proposes a new and original FPGA architecture with testability facilities. It is first demonstrated that classical FPGA architectures do not allow one to efficiently implement sequential circuits with a scan chain. It is consequently proposed to modify the architecture of classical FPGAs in order to create an implicit-scan chain into the FPGA itself called implicit scan FPGA (IS-FPGA). Using this new FPGA architecture, any sequential circuit implemented into the FPGA is 'implicitly scanned'. An original and optimal implementation of the proposed architecture is given with minimum area overhead and absolutely no delay impact. Additionally the technique is transparent for the user as well as for the FPGA mapping tools. Finally, it is demonstrated that the implicit-scan concept allows 'over-scan' of sequential circuits resulting in highly testable circuits.

We study the voltage and current behavior of Gate Oxide Short faults due to pinholes in the gate oxide. Our objective is to give a detailed analysis of the behavior of the GOS defect taking into account random parameters such as the GOS resistance, the GOS location and the GOS size. To facilitate an accurate analysis, we use a bi-dimensional array, and, since a complete analysis is desired, we derive characteristics of the GOS as a function of its resistance, location and size. Finally, we validate the model has been validated through measurements of GOS intentionally injected into a designed and manufactured circuit.

This paper presents a high-quality and area-efficient ramp generator to be used for on-chip testing of analog and mixed-signal circuits. An original adaptive scheme is developed to palliate the inaccuracy of a basic ramp generator. As a result, the proposed adaptive ramp generator exhibits very good performances in terms of slope precision and ramp linearity while maintaining a low area overhead.

This paper focuses on the detectability of defects causing the gates of transistors in CMOS integrated circuits to float (open), i.e., on floating gate transistor (FGT) faults. Such faults are known to occur in practice. It is increasingly important to consider their detection to meet high quality requirements for circuits fabricated in deep submicrometer technologies. We focus on the detectability of FGT faults by the standard voltage- and current-based production test strategies that we refer to as static voltage (SV), dynamic voltage (DV), and static current (SC) test strategies. We demonstrate how the behavior of the devices caused by FGT faults depends on two classes of technological and topological parameters: the predictable and unpredictable parameters. We show that an FGT fault can induce abnormal logic values, additional delays, or increased power supply current. We introduce the concept of a detectability interval, i.e., the range of values an unpredictable parameter may assume that one allows for the fault detection using a specific test strategy. We illustrate how the detectability intervals for the SV and DV strategies complement that of the SC strategy. In addition, a new test scheme that results in an increased SC detectability of FGT faults is developed. Finally, we demonstrate the effects of initial trapped charges and the effects of coupling to surrounding metal on the detectability intervals of each of the test strategies.

This paper describes a method to obtain a temperature independent analog BIST. The test procedure is based on the reuse of existing analog circuits, configured either as stimuli generators or as signature analyzers. The paper explains the general problem of temperature deviation present in analog BIST, and shows an approach to overcome this limitation, validated by simulation results.

The objective of this paper is to generate an Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault." Then, it is commented that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is also commented that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.

The objective of this paper is to discuss the possibility of reusing the existing hardware originally present in an analog application to implement test functions for a completely autonomous self-testable solution. In this first approach, a 8/sup th/ order analog linear filter is used as an application example. The required modifications in the circuit are presented with the results in terms of area overhead and fault coverage.

In this paper, we describe an experiment about structural testing of two XILINX FPGAs families. In our practical approach, the FPGA is divided into different arrays: an array of logic cells, an array of interconnect cells and an array of RAM cells. For each part, we use a specific fault model and we generate test configurations and test vectors for the considered models. In each case, for each array, we try to minimize as much as possible the number of test configurations because re-programming FPGAs is really time consuming.

The paper proposes a BIST approach for deriving the main characterization parameters of ADCs from histogram data. An adequate choice of input stimuli and time decomposition scheme is proposed in order to minimize the extra on-chip hardware required to extract these parameters. The idea of time decomposition consists in replacing classical hardware-consuming concurrent calculations by hardware-saving time-spread calculations. The decomposition technique is used both at high level (specific test phases are dedicated to each ADC parameter computation) and low level (sequential steps inside each test phase). Pseudo-algorithms are given to derive offset, gain error and nonlinearities.

This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA. The proposed approach is applied to the XILINX SPARTAN, 4000 and 3000 families. On these examples of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then for a single logic cell, and finally for the m/spl times/m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configurations for a single logic cell. An approach is then described to define a minimum number of test configurations for a logic cell knowing the test configurations of its logic modules. This approach gives only 4 test configurations for the XILINX Spartan, 5 for the 4000 and 4 for the 3000 while the previous published works concerning Boolean testing of these FPGA families give 8 for the 4000 and 5 for the 3000.

The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. In usual SRAM-based FPGAs, Configurable Interface Modules (CIMs) can be found between the global interconnect and inputs of the logic cells (input CIMs) or between output of the logic cells and the global interconnect (output CIMs). It is demonstrated that an input CIM that connects N/sup in/ segments to a logic cell input requires N/sup in/ test configurations and that an output CIM that connects a logic cell output to N/sup out/ segments requires 2 test configurations. Then, it is proven that a set of K/sup in/ input CIMs can be tested in parallel making the number of required test configurations equal to N/sup in/. In the same way, a set of K/sup out/ output CIMs is shown to require only 2 test configurations if N/sup out/>K/sup out/. Finally, it is shown that the complete mXm array of logic cells with K/sup in/ input CIMs and K/sup out/ output CIMs can be tested with only N/sup in/ test configurations using the XOR tree and shift register structures.

This paper studies the Boolean (Static Voltage) and the I/sub ddq/ (Static Current) detection of Floating Gate faults due to large opens on transistor gate connections. We show that existing electrical models describing the behavior of FGT faults fail to allow the prediction of the floating gate potential due to the unpredictable parameters such as the initial changes and the polysilicon-to-bulk capacitance. We propose the twin-transistor structure as a basis for a general analysis of the Boolean and I/sub ddq/ detection of FGT faults. Using this analysis, optimal conditions for detection are defined for Boolean as well as I/sub ddq/ tests.

In this paper, a cost-effective DFT solution for the testing of ring oscillator-based VCOs is presented. The strategy is based on the reconfiguration concept: we propose to modify the circuit so that the VCO operates as a digital structure in test mode. The test can then be performed on a standard digital tester, avoiding the use of costly mixed-signal test equipment. In addition, simulation results show that the use of an adequate digital test strategy permits one to obtain better fault coverage than a classical functional center frequency test.

This paper studies the detectability of MOS floating gate transistor faults considering classical static voltage, dynamic voltage and static current strategies. The behavior of the defect depends on two classes of parameters: the predictable and unpredictable parameters. A floating gate fault can induce abnormal logic values, additional delays, or increased power supply current. Consequently, classical test strategies can only detect floating gate faults for a given range of the unpredictable parameter. Here, a new test scheme is proposed, which allows a considerable current to flow in the stable state making the circuit with a floating gate I/sub DDQ/ testable. It is shown that a combination of voltage and current testing can ensure 100% detection of the floating gate defects, i.e., regardless of the unpredictable parameters. Analysis with increasing initial charge on the floating gate transistor shows how the detectability intervals become smaller for the voltage testing strategies and increase for the static current strategy.

In this paper, a BIST scheme is proposed that applies to any kind of SI building blocks constituted of an aggregate of identical memory cells. The fundamental idea is to reconfigure the building block into a cascade of memory cells so that the output current is equal in magnitude to the input current. Using a very simple circuitry, an error current can then easily be generated that permits one to detect faults in the block.

This paper address the problem of testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. The Configurable Interface Modules (CIMs) are assumed to be implemented with FPGA multiplexers but the results can be easily extended to any type of interface module. First, it is demonstrated that an address bit Configurable Interface Multiplexer requires N=2/sup n/ test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable Interface Modules with n address bits is analysed and it is proven that the set of CIMs can be tested in parallel making the number of required test configurations equal to N=2/sup n/. Third, it is shown that the complete circuit, i.e. a m/spl times/m array of sets of k Configurable Interface Multiplexers with n address bits can be tested with only N=2/sup n/ test configurations using the XOR tree and shift register structures.

This paper presents a novel technique for testing Field Programmable Gate Arrays (FPGAs), suitable for use in the case of frequent FPGA reuse and rapid dynamic modifiability of the implemented function.

The paper describes an approach to optimize the application of the multi-configuration DFT technique for analog circuits. This technique allows to emulate the circuit in a number of new test configurations targeting the maximum fault coverage. The brute force application of the multi-configuration is shown to produce a very significant improvement of the original poor testability. An optimized approach is proposed to apply this DFT technique in a more refined way. The optimization problem consists in choosing among the various permitted test configurations, a set that leads to the best testability/cost trade-off. This set is selected according to ordered requirements: (i) the fundamental requirement of maintaining the maximum fault coverage and (ii) non-fundamental requirements of satisfying some user-defined cost functions such as test time, silicon overhead or performance degradation. Results are given that exhibit very interesting features in terms of either test procedure simplicity or DFT penalty reduction.

This paper proposes a methodology for testing the configurable logic of RAM-based FPGAs taking into account the configurability of such flexible devices. The methodology is illustrated using the XILINX 4000 family. On this example of FPGA, we obtain only 8 basic test configurations to fully test the whole matrix of CLBs. In the proposed test configurations, all the CLBs have exactly the same configuration forming a set of one-dimensional iterative arrays. The iterative arrays present a C-testability property in such a way that the number of test configurations 8 is fixed and independent of the FPGA size.

This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2/sup N/ memory cells is proposed taking into account the LUT and RAM modes. Concerning the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the march tests. We also propose a unique test configuration called 'pseudo shift register' for mxm arrays of modules. In this configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called 'shifted MATS++' is described. Concerning the LUT mode, we use the concept of non-redundant test that proposes to test in LUT mode the parts of the module not tested in RAM mode. Under this hypothesis, it is demonstrated that the test of a single module as well as the test of an mxm array of modules require only 3 test configurations. Using our solution, the test of a complete array of mxm LUT/RAM modules requires 4 test configurations independently of the size of the array and of the modules.

In this paper a DFT technique is proposed that provides the full controllability and observability of each memory cell of a switched-current circuit. The technique is proven to be applicable to any kind of SI circuits, very easy to automate and without any impact on the circuit performance. Indeed, the hardware configuration of the circuit is preserved and only the timing configuration is managed to convert the circuit into a fully testable structure in test mode.

The test of the Configurable Logic Blocks of RAM based FPGAs under a Stuck-At fault model has been studied. The high cost of changing the configuration, by reprogramming the FPGA during testing, forces a strategy to reduce the number of different configurations used for testing purposes. After finding the optimal solutions for the elementary structures of the Logic block, Multiplexers and Look-Up Tables, the problem of testing interconnected elementary structures is addressed. The method is illustrated using an elementary structure and then applied to a popular FPGA (XILINX 3000 family) where a reduced set of configurations (5) and their corresponding test sequences is found to cover all (100%) the Configurable Logic Block faults modelled.

This paper demonstrates that the detection of defect depends on two classes of parameters: the predictable and unpredictable parameters. The demonstration is made with two very different types of defects (the interconnect short and the interconnect open) considering the static voltage, dynamic voltage and static current strategies. The value of the short resistance is the unpredictable parameter of the interconnect short and the polysilicon-to-bulk capacitance of the interconnect open. It is shown that any test strategy is able to detect shorts and opens each one for a given range of the unpredictable parameter called the 'analog detectability interval'. It is then demonstrated that the fundamental criterion for test strategy efficiency evaluation is the consideration of the analog detectability Intervals together with the unpredictable parameter distributions. It is finally shown that for realistic situations the voltage strategies exhibit a very good efficiency for a very reasonable cost making the use of expensive current strategy difficult to justify.

This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrated that a set of only 3 Test Configurations called the Orthogonal, the Diagonal-1 and Diagonal-2 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant. Then the test of each configuration is shown equivalent to the test of classical buses. The final proposed Manufacturing Test Procedure present a constant number of Test Configurations (3) and very short Test Sequences.

A Design-For-Testability (DFT) technique for analog circuits, called the Multi-Configuration technique is presented. This technique exhibits some flexibility features since different solutions are possible for its implementation. Different degrees of granularity are associated to the different solutions, corresponding to a given trade-off between implementation cost and test and/or diagnosis facilities. The multi-configuration technique is illustrated and validated on a 8/sup th/ order band pass filter.

This paper analyses the impact of the power supply voltage on the logical behavior of resistive Bridging Fault. It is theoretically demonstrated that the interval of resistance corresponding to the appearance of a faulty value exponentially increases when the power supply decreases. Using the Parametric Model specifically developed for resistive bridging faults, results of parametric bridging faults simulations on benchmark circuits clearly show an improvement of about 40% when a lower-than-normal power supply is used. Moreover this bridging fault coverage improvement technique doesn't need any additional effort such as Design for Testability or specific Test Pattern Generation.

The majority of design for testability (DFT) methods for sequential circuits are based on scan designs (complete or partial). Nevertheless, with these methods the test application time remains often prohibitive due to the long shift operation to enter the test vector into the scan register. In this paper, we present a DFT method which modifies the circuit in such a way that, during the test operation, several more easily testable configurations are emulated. Different implementations are proposed for these test configurations that are shown to be useful to improve either the controllability or the observability. The efficiency of the method is evaluated in terms of fault coverage, number of modified flip-flops and test application time, using ISCAS89 benchmarks.

This paper concerns the test of mixed-signal circuits. A novel DFT approach for analog parts constituted of several op-amp-based modules is presented. The idea is to bring the testability resources (controllability and observability) on the frontier of each embedded module by creating transparent paths between external and local I/O's. The key point of this transformation is to permit each analog stage to have a test mode for which it is converted into a follower stage. Adaptative solutions are proposed depending of the availability of on-chip digital resources eventually re-usable to manage analog test. The testability cost is shown to be very low in terms of additional circuitry, number of extra pins, analog response penalty and test management. A case study is presented that demonstrates the applicability of the method.

The most recent bridging fault models, the voting and the biased voting model use the concept of relative transistor strength during fault simulation. A SPICE pre-simulation allows one to determine the relative strength of unit dimension transistors; the results stored in tables are then used during fault simulation. This concept is very efficient for single transistor and parallel transistor networks but suffers when serial transistor networks are considered. The relative strength of serial transistor networks implies the use of many tables (for 2, 3, 4, ... serial n and p transistors) slowing down the fault simulation procedure. This paper presents a new model for serial transistor networks which accelerates bridging fault simulation. This model allows one to easily define a single transistor equivalent to the serial network. In this way, any bridging fault involving any transistor network can be considered as a bridging fault involving single transistors. This model used with either the voting or the biased voting model decreases the number of required tables increasing the efficiency of the bridging fault simulation.

From circuit measurement, it has been demonstrated that actual bridging faults have an intrinsic resistance mainly in the range from 0 /spl Omega/ to 500 /spl Omega/. This paper first analyses the consequences of this resistance on the electrical and logic behavior of bridging faults. Second, it is demonstrated that the classical models such as the voting model which consider the resistance as negligible, do not accurately and realistically represent the behavior of the fault. Third, a new parametric bridging fault model is proposed allowing to realistically represent the faulty behavior according to the intrinsic resistance which is not known a priori. Finally, a parametric bridging fault simulation algorithm is described together with some redefinition of the classical concepts of fault detection and fault coverage.

This paper analyses the general problem of the determination of the intermediate potentials created by a bridging fault. The analyses is made taking into account the bridge resistance value. It is shown that the fault is detectable as a logic error for a given range of bridge resistance values. But, in this range, the logic faulty value is independent of the bridge resistance value. A general electrical model which can be used to determine if a particular structure of transistors gives an intermediate voltage which is higher or lower than a given threshold voltage is proposed. A global procedure to simulate bridging fault is given. By using the proposed equations and model no SPICE simulation is required.>

Sequential ATPGs, now, are able to handle an appreciable degree of sequentiality, thus allowing to treat partial scan implementations with a suitable fault coverage. Nevertheless, with these methods the test duration remains often prohibitive due to the long scan register. The DFT method we present is based on cycle breaking and sequential depth reduction guided by graph analysis. When a flip-flop is recognized as a pertinent site for breaking cycles, its input line is disconnected. The observability and controllability losses induced by this operation are compensated by the creation of overlapping configurations guided by structural analysis. Results are presented on testability improvement. They illustrate the drastic cycle and sequential depth reduction obtained when passing from an initial circuit to its corresponding configurations. An implementation of the method using scan flip-flops as modified instances is proposed. Comparison with purely scan techniques is presented in terms of fault coverage, test length and number of modified flip-flops.>

It is demonstrated that a floating gate transistor (FGT) is influenced by its topological environment. The equivalent gate-to-source voltage of the FGT depends on the initial charges trapped in the gate oxide, the surrounding potential of metal lines and the drain-to-source voltage of the FGT itself. An electrical study of the floating gate fault is presented. A theoretical model taking into account the influence of the transistor's environment is proposed. Analytical expressions for the equivalent gate-to-source voltage are derived, and the FGTs electrical operation mode is analyzed. This model is validated by SPICE simulations and by actual device measurements. The problem of testing for FGTs is discussed.>