The performance of narrowband active noise control (ANC) systems degenerates significantly under the frequency mismatch between the synthesized reference signal and the primary noise. This paper proposes a new narrowband ANC system that incorporates a frequency corrector for the internal reference signal generator to mitigate the ill-effects caused by the frequency mismatch. The proposed frequency estimator uses the iterative frequency estimation algorithm based on the minimum variance distortionless response spectrum that has advantages of accuracy and fast convergence. The performance of the new narrowband ANC system is analyzed under the conditions of frequency mismatch and the secondary-path phase estimation error. The frequency and amplitude of the primary noise are modeled as time-varying variables in the theoretical analysis. Computer simulations are conducted to demonstrate the performance of the new ANC system and to verify the analysis results.

This paper proposes two new signal detection methods, which are based on the ordered successive interference cancellation (OSIC) algorithm, for spatially multiplexed multiple input multiple output (MIMO) systems. By using an enhanced version of the OSIC algorithm, one of the proposed methods significantly improves the performance of the original OSIC algorithm, while slightly increasing the hardware complexity. The other proposed method combines the enhanced SIC algorithm with multiple ordering technique of the channel matrix. This new method is especially useful in soft decoding MIMO systems since it can generate the log likelihood ratio (LLR) values without using any LLR estimation methods. The simulation and implementation results show that the proposed detectors provide very good solutions for both hard and soft decoding MIMO systems.

This paper presents an efficient method for implementing the Discrete Cosine Transform (DCT) with distributed arithmetic. While conventional approaches use the original DCT algorithm or the even-odd frequency decomposition of the DCT algorithm, the proposed architecture uses the recursive DCT algorithm and requires less area than the conventional approaches, regardless of the memory reduction techniques employed in the ROM Accumulators (RACs). An efficient architecture for implementing the scaled DCT with distributed arithmetic is also proposed. The new architecture requires even less area while keeping the same structural regularity for an easy VLSI implementation. A comparison of synthesized DCT processors shows that the proposed method reduces the hardware area of regular and scaled DCT processors by 17 percent and 23 percent, respectively, relative to a conventional design. With the row-column decomposition method, the proposed architectures can be easily extended to compute the two-dimensional DCT required in many image compression applications such as HDTV.