This paper presents the analysis and a proof-of-concept design of the low-complexity early termination hybrid automatic repeat request (ET-HARQ) for ultra-reliable low-latency communication (URLLC). In ET-HARQ, unfit packets are flagged for retransmission prior to decoding, a process that significantly diminishes decoding complexity and facilitates swift HARQ reporting. This characteristic makes ET-HARQ well-suited for URLLC applications. We analyze the impact of ET-HARQ on the packet error rate (PER), throughput, and complexity performance in the finite block length regime, taking into consideration cyclic redundancy check (CRC) limitations. Numerical results indicate that ET-HARQ significantly reduces the decoding complexity and improves throughput with little to no loss in the PER. In addition, ET-HARQ demonstrates resilience even with a short CRC, whereas the imperfections of a short CRC significantly impact PER reliability in standard HARQ. To validate our analysis, we also design a practical early termination mechanism involving belief propagation and neural network (BP-NN) to predict the decodability of the received packet. Testing with BCH and CRC-polar codes shows that it can reach up to a 70 % ∼ 80 % prediction accuracy with packet lengths less than 128 bits encoded with high-density linear block codes. Simulation shows that the BP-NN-based ET-HARQ has significantly lower complexity at this accuracy level than the standard HARQ with similar reliability.

We propose real-time remote estimation of a dual-process status update system for mission-critical applications using non-orthogonal multi-access (NOMA) and orthogonal multi-access (OMA) techniques. We consider the finite block length regime so that, with OMA, the status updates of each process are transmitted using time slot sharing. Meanwhile, with NOMA, we use a power domain packet combining to allow simultaneous status updates of each process in each time slot. To compensate for the reliability loss due to short packet lengths and multi-access, we utilize packet retransmission with hybrid automatic repeat request (HARQ). Specifically, we propose OMA-HARQ and NOMA-HARQ transmission control policies, where multi-access resource sharing is jointly designed with HARQ. We propose dynamic and static scheduling policies by optimizing time-sharing or power-sharing ratios between sensors over time. The dynamic policy utilizes higher flexibility to optimize the reliability under restricted age-of-information (AoI), leading to the best estimation mean-squared-error (MSE) performance. We formulate and solve policy optimization problems, where both long-term average MSE and its variance minimization are the targets. We obtain optimal policies to minimize the composite objective function of costs of each process using the Markov decision process (MDP) framework and relative value iteration algorithm. An intensive simulation study shows significant performance improvement over existing approaches.

The fifth generation (5G) of mobile standards is expected to provide ultrareliability and low-latency communications (URLLC) for various applications and services, such as online gaming, wireless industrial control, augmented reality, and self driving cars. Meeting the contradictory requirements of URLLC, i.e., ultrareliability and low latency, is considered to be very challenging, especially in bandwidth-limited scenarios. Most communication strategies rely on the hybrid automatic repeat request (HARQ) to improve reliability at the expense of increased packet latency due to the retransmission of failing packets. To guarantee high reliability and very low latency simultaneously, we enhance the HARQ retransmission mechanism to achieve reliability with guaranteed packet-level latency and in-time delivery. The proposed nonorthogonal HARQ (N-HARQ) utilizes nonorthogonal sharing of time slots for conducting retransmission. The reliability and delay analysis of the proposed N-HARQ in the finite block length (FBL) regime shows very high performance gain in packet delivery delay over conventional HARQ in both additive white Gaussian noise (AWGN) and Rayleigh fading channels. We also propose an optimization framework to further enhance the performance of N-HARQ for single and multiple retransmission cases.

In this paper, a non-orthogonal hybrid automatic re-peat request (N-HARQ) packet transmission strategy is proposed for ultra-reliable delay sensitive communications. As opposed to conventional HARQ, where retransmission of the failing packet is provided in new time slots, in the proposed scheme, retransmission of the packet is served together with the next arriving packet. Using N-HARQ, we avoid the queuing delay due to retransmission and reduce the packet arrival delay. We consider the short block length regime and analyze the error rate, throughput and delay performance of N-HARQ using the Markov model. Simulation results show that the proposed scheme achieves superior performance in providing packet arrival delay guarantee in comparison to its baseline orthogonal HARQ (O-HARQ).

This paper presents dynamic reconfiguration of a register file of a Very Long Instruction Word (VLIW) processor implemented on an FPGA. We developed an open-source reconfigurable and parameterizable VLIW processor core based on the VLIW Example (VEX) Instruction Set Architecture (ISA), capable of supporting reconfigurable operations as well. The VEX architecture supports up to 64 multiported shared registers in a register file for a single cluster VLIW processor. This register file accounts for a considerable amount of area in terms of slices when the VLIW processor is implemented on an FPGA. Our processor design supports dynamic partial reconfiguration allowing the creation of dedicated register file sizes for different applications. Therefore, valuable area can be freed and utilized for other implementations running on the same FPGA when not the full register file size is needed. Our design requires 924 slices on a Xilinx Virtex-II Pro device for dynamically placing a chunk of 8 registers, and places registers in multiples of 8 registers to simplify the design. Consequently, when 64 registers is not needed at all times, the area utilization can be reduced during run-time.

In this paper, we present the design and implementation of a BRAM-based multiported register file with arbitrary number of read and write ports. In order to avoid the conflicts associated with write ports, we present a register renaming technique that is applied between the compiler and the assembler. This technique enables the utilization of a banked-BRAM register file as a true multiported register file. The advantage is that we do not need to modify the compiler nor the assembler and the technique is scalable. A register file with the register renaming technique has the highest performance, requires fewer resources and consumes less power compared to other approaches. As a case study, we applied our technique to the configurable open-source ρ-VEX VLIW processor. We implemented a 64 × 32-bit, 4-write and 8-read ports register file utilizing BRAMs for a 4-issue ρ-VEX processor. This register file with register renaming saves 9109 Xilinx Virtex-4 FPGA slices by just utilizing 32 BRAMs compared to a pure slice-based register file with no effect on the overall frequency of the processor as well as the cycle count for any application.