Neuronflow is a neuromorphic, many core, data flow architecture that exploits brain-inspired concepts to deliver a scalable event-based processing engine for neuron networks in Live AI applications. Its design is inspired by brain biology, but not necessarily biologically plausible. The main design goal is the exploitation of sparsity to dramatically reduce latency and power consumption as required by sensor processing at the Edge.

Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which stacks voltage domains in a design, can effectively improve the power delivery efficiency and thus improve battery lifetime. However, such an approach requires balanced current between different domains across multiple operating scenarios. Furthermore, level shifter insertion (together with shifters' delay impacts), along with placement constraints imposed by power domain regions, can incur power and area penalties. To our knowledge, no existing work performs sub-block-level partitioning optimization for stacked-domain designs. In this paper, we present an optimization framework for stacked-domain designs. Based on an initial placement solution, we apply a flow-based partitioning that is aware of multiple operating scenarios, cell placement, and timing-critical paths to partition cells into two power domains with balanced current and minimized number of inserted level shifters. We further propose heuristics to define regions for each power domain so as to minimize placement perturbation, as well as a dynamic programming-based method to minimize the area cost of power domain generation. In an updated floorplan, we perform matching-based optimization to insert level shifters with minimized wirelength penalty. Overall, our method achieves more than ~10% and 3X battery lifetime improvements in function and sleep modes, respectively.

This paper presents the results of research into the application of an active battery switching system in an electric vehicle's drivetrain. The system's purpose is to increase the drivetrain's electrical efficiency, especially in the partial-load range. Efficiency is increased using a switching system that allows the vehicle's traction-battery circuitry to be changed during operation, thereby adjusting the intermediate circuit voltage to that actually required. The system consists of three electronic switches, which allow two different voltages in the intermediate circuit. This paper presents possible operating strategies of the new system developed from roller dynamometer test runs.

Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which connects voltage domains in series, can effectively improve power delivery efficiency and thus improve battery lifetime. However, such an approach requires balanced currents between different domains across multiple operating scenarios. Furthermore, level shifter insertion, along with placement constraints imposed by power domain regions, can incur significant power and area penalties. To the best of our knowledge, no existing work performs subblock-level partitioning optimization for stackeddomain designs. In this paper, we present an optimization framework for stacked-domain designs. Based on an initial placement solution, we apply a flow-based partitioning that is aware of multiple operating scenarios, cell placement, and timing-critical paths to partition cells into two power domains with balanced cross-domain current and minimized number of inserted level shifters. We further propose heuristics to define regions for each power domain so as to minimize placement perturbation, as well as a dynamic programming-based method to minimize the area cost of power domain generation. In an updated floor plan, we perform matching-based optimization to insert level shifters with minimized wirelength penalty. Overall, our method achieves an excellent current balance across stacked domains with less than 10% discrepancy, which results in up to more than 2× battery lifetime improvements.

Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and VDD, and the memory "on top of it" between VDD and 2VDD, creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in "stacked mode" of 96%.

Modern systems for ubiquitous computing domains such as Internet-of-things (IoT), wearable computing etc. are characterized by low duty cycle, low operating and stand by power consumption requirements. The design of such systems is further constrained by increasing leakages due to technology scaling and/or increased data retention requirements. These conflicting requirements make leakage reduction of digital logic and SRAM a primary objective for efficient system realization. In this work, we discuss the effectiveness of advance leakage reduction techniques in 40nm (HYT technology) for SRAM and digital logic. For SRAM memory, adding error correction coding (ECC) to the memory subsystem can provide new trade-offs which will be advantageous for these low-duty cycle systems. We show that decreasing the data retention voltage while preventing errors using ECC will help decrease the leakage current by 45% (leakage power by 70% for SRAM). For the digital logic, test and simulation data shows that reverse body biasing (RBB) can reduce the logic leakage current by ~3x in the worst case process and temperature conditions. However, it should be carefully implemented as RBB causes increase in leakage current at nominal temperatures due to higher junction currents. Moreover, the asymmetric biasing where PMOS is biased by 0.7V and NMOS by 0.3V provides optimum results. RBB can also help reducing the switching energy at low frequency due to increased contribution of leakage to total energy compare to conventional technologies. We also show that increasing the gate length by 20% can help reduce the leakage current by 2x while there is minimal penalty on dynamic power and speed. Combining the asymmetric RBB application and increased gate-length can result in ~6x leakage reduction.

Wheel speed sensor is commonly used in conventional Antilock Braking Systems (ABS) to measure the wheel rotational speed. This paper proposes a novel architecture for In-Wheel Electric Vehicles (EVs) based on data fusion concept that provides improved accuracy, reliability, redundancy and fault-tolerance for the wheel speed measurement system of the ABS. The proposed method was extensively evaluated using actual ABS hardware. The experimental results showed that the accuracy of the wheel speed estimation based on the proposed data fusion were improved by up to 46 percent in comparison with a commercial ABS sensor. The proposed approach has the potential to substantially improve the performance of the ABS for In-Wheel EVs.

We present a design framework for wirelessly powered generic computing platforms that takes into account various system parameters in response to a time-varying energy source. These parameters are the charging profile of the energy source, computing speed (fclk), digital supply voltage (VDD), energy storage capacitance (Cs), and power conversion efficiency (η). We address both continuous and discrete operational modes of computation based on the energy source's charging profile. Unlike other reported works where investigations are limited to wireless energy transfer and functional demonstrations, our aim is to develop a theoretical model that comprises the complete system architecture by combining energy transfer and consumption in a step-by-step manner. We show that field resilience operation in a wireless energy field can be incorporated by modulating the power consumption in the digital platform in response to changing energy fields using this analysis. This paper also allows guidelines for choosing the appropriate computing policies based on the charging profile of energy source. This leads to an optimal, adaptive use of available energy in order to optimize the overall performance.