This paper introduces an ultra-low-power and area-efficient switching scheme for differential input SAR ADCs with top-sampling technique. The proposed scheme offers a constant common-mode voltage at the comparator input and maintains symmetrical DAC switching across the conversion cycle, making the architecture insensitive against comparator offset voltage variations. The switching operation reduces the total area of the capacitor DAC by 75 % and achieves a 100 % switching energy saving with respect to conventional SAR switching. Simulation results from a behavioral model of a 10-bit SAR ADC using Verliog-A description demonstrate the effectiveness of the proposed solution.

Fast settling, accurate reference voltage buffer (RVB) are one of the key blocks of a successive approximation register (SAR) ADC. This paper presents the design of a RVB, which is aimed to drive SAR ADC architectures with hybrid RC-DAC: a popular implementation for area and power efficient solution. The design challenges associated with the RVB implementation are also discussed using a 12-bit, 8MSPS SAR ADC as a test vehicle. Implemented in 130 nm CMOS process, the buffer operates from a 1.2 V supply and consumes 760 μA current while occupying 1530 μm2of area. It is capable of settling to better than 12-bit accuracy within 3.9 ns and has a total output noise of 87 μV. Post-layout simulations together with the entire SAR ADC shows a ENOB of 11.5-bits thus confirming that the proposed reference voltage buffer serves the targeted application.

Multistage operational amplifiers suitable for nanometer-scale CMOS technologies and low-voltage applications are described. The low intrinsic gain of transistors is compensated for with cascade of single-stage amplifiers. Techniques for compensations are revisited and the optimal solution identified. An example of a novel scheme that achieves 67 dB of DC gain, 320 MHz of bandwidth and 61 degrees of phase margin is presented. The power consumption is as low as 0.24 mW with a slew rate of 84.5 V=µ s. The CMOS technology is 65 nm; the design uses only minimum channel length transistors.

This paper proposes a new low order time variant digital ΣΔ MASH modulator for fractional frequency synthesizers. The phase noise spectrum is improved as the spur tones from the fractional modulation are disabled. The usage of low order time variant MASH architectures reduces the number of levels that control the programable divider, reducing therefore the complexity and power requirements of the synthesizer.

An architecture for low-power ΔΣ modulators suitable for high-resolution portable sensor systems is presented. The circuit uses a single operational amplifier to achieve a third-order noise shaping. The two-stage op-amp employs a boosting technique that increases by 5 the slew-rate. The circuit, simulated at the transistor level using a conventional 0.18-μm CMOS technology, obtains a peak SNDR of 88 dB over an input signal bandwidth of 100 kHz. The simulated power consumption is 125 μW with a 1.5-V supply voltage. The achieved Figure of Merit (FoM) is 31 fJ/conversion-level.

A double sampled second order ΣΔ modulator with an analog look ahead (ALA) approach is presented. The proposed architecture provides an extra clock period to be used for the quantization. The feedforward path in both integrators allows the further reduction of the output voltage swing, relaxing also the slew-rate requirements of the op-amps. Moreover, the modulator enables the reduction of the number of quantization levels in the quantizer, thus the overall power consumption of the modulator would be significantly reduced. The proposed solution has been simulated at behavioral level by considering an improved model which takes into account the slew-rate and bandwidth limits.

A two stage op-amp with an effective technique to enhance slew-rate and gain is presented. The enhancement is provided by an auxiliary monitor circuit which is activated in slewing conditions, but can contribute to the gain in normal conditions. The amplifier, simulated in a 0.18 Omegam technology, achieves 74 dB DC gain, 160 MHz bandwidth and 26.8 V/mus slew-rate for a load capacitance of 1.75 pF with 362 muW power consumption, considering a supply voltage of 1.8 V.