Automatic synthesis of analog and Radio Frequency (RF) circuits is a trending approach that requires an efficient circuit modeling method. This is due to the expensive cost of running a large number of simulations at each synthesis cycle. Artificial intelligence methods are promising approaches for circuit modeling due to their speed and relative accuracy. However, existing approaches require a large amount of training data, which is still collected using simulation runs. In addition, such approaches collect a whole separate dataset for each circuit topology even if a single element is added or removed. These matters are only exacerbated by the need for post-layout modeling simulations, which take even longer. To alleviate these drawbacks, in this paper, we present FuNToM, a functional modeling method for RF circuits. FuNToM leverages the two-port analysis method for modeling multiple topologies using a single main dataset and multiple small datasets. It also leverages neural networks which have shown promising results in predicting the behavior of circuits. Our results show that for multiple RF circuits, in comparison to the state-of-the-art works, while maintaining the same accuracy, the required training data is reduced by 2.8x - 10.9x. In addition, FuNToM needs 176.8x - 188.6x less time for collecting the training set in post-layout modeling.

Machine Learning (ML) has shown promising results in predicting the behavior of analog circuits. However, in order to completely cover the design space for today’s complicated circuits, supervised ML requires a large number of labeled samples which is time-consuming to provide. Furthermore, a separate dataset must be collected for each circuit topology making all other previously gathered datasets useless. In this paper, we first present a database including labeled and unlabeled data. We use neural networks to determine the behavior of complicated topologies by combining the more simple ones. By generating such unlabeled data, the time for providing the training set is significantly reduced compared to the conventional approaches. Using this database, we propose a fully-automated analog circuit generator framework, AnGeL. AnGeL performs all the schematic circuit design steps from deciding the circuit topology to determining the circuit parameters i.e. sizing. Our results show that for multiple circuit topologies, in comparison to the state-of-the-art works while maintaining the same accuracy, the required labeled data is reduced by 4.7x - 1090x. Also, the runtime of AnGeL is 2.9x - 75x faster.

Recently, there have been many studies attempting to take advantage of advancements in Artificial Intelligence (AI) in Analog and Mixed-Signal (AMS) circuit design. Automated circuit sizing optimization and improving the accuracy of performance models are the two predominant uses of AI in AMS circuit design. This paper first introduces and explains the basic concepts in AI especially the ones that are more suitable to this application. Next, it surveys some recent studies of various AI techniques for AMS circuit design. Then, it discusses the main approaches as well as the pros and cons of each method. Finally, it gives meaningful insights about the current challenges and open issues, as well as recommends approaches for specific applications.

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, -3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with VDDof 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area.

A new framework for secure communication in physical layer is proposed. A network of users equipped with coupled dynamical systems is considered. The aim is to securely exchange messages between network nodes in the presence of an eavesdropper, referred to as Eve. Unlike a traditional wireless system, the messages to be conveyed are not sent directly through the medium. Instead, they are mapped to initial conditions of the dynamical system. Once the system converges to a steady state, conditions of the local system at each node is measured to recover the sent messages. A fundamental property of the proposed system which makes it secure is that Eve is not part of the dynamical system and hence, she does not observe the initial conditions of the nodes for steady state comparison measurement. In particular, a situation with two users is considered. The proposed system is then modeled as a two-way wiretap channel and the secrecy capacity region is derived under various conditions. A consequence of our result is that regardless of Eve's physical location and how strong her receiver is the achievable rates are positive, i.e., secure communication is possible. Furthermore, a radio frequency (RF) system is proposed to realize this model in a wireless setting by means of local coupled oscillators. In particular, a unidirectional master-slave coupling architecture is considered where a power-constrained slave node synchronizes its frequency with a high-power master node. It is shown how the coupling mechanism, realized by transmitting and receiving power between the RF front-ends of the master and the slave node, can be used by the slave node to securely send messages or to share secret keys with the master node. To the best of our knowledge, this is the first architecture providing physical layer secret key generation fully designed in the RF front-end. The proposed RF system is simulated using Advanced Design System (ADS). The simulation results are shown for a 10m channel link and confirm the security condition. The secret key generation rate is 2 bits per synchronization time-frame which is dominated by the wave propagation delay between the two nodes.

In this letter, we present a new coherence-based performance guarantee for the orthogonal matching pursuit (OMP) algorithm. A lower bound for the probability of correctly identifying the support of a sparse signal with additive white Gaussian noise is derived. Compared to previous research work, the new bound takes into account the signal parameters, such as dynamic range, noise variance, and sparsity. Numerical simulations show significant improvements over previous research work and a closer match to empirically obtained results of the OMP algorithm.

We introduce a novel technique of phase matching and phase compensation in resonator-based millimeter wave passive filters to broaden the bandwidth and increase the center frequency. Phase matching and compensation is implemented using effective negative group index (NGI) structures. All the important parameters of NGI structure are found using proposed analysis. The insertion loss of filter without any effective NGI effect is less than ldB and return loss is around 25dB with center frequency of 38GHz and bandwidth of 40GHz. The insertion loss of NGI enhanced filter is around 2dB and return loss is around 18dB with center frequency of 60GHz and bandwidth of 60GHz. To the best of our knowledge, the insertion loss performance is the best reported results for broadband mm-wave passive filters implemented on CMOS process using lumped circuit elements. All the simulation are performed on a 0.13/im CMOS process and we found a good agreement between analysis and simulation results.

In this paper we introduce a novel Analog-to-Digital architecture for high speed applications that is compatible with digital CMOS and surpasses the issues with traditional voltage conversion techniques. The quantization method is based on the delay-to-digital concept as a means to quantize a variable delay line. A 4 bit 1 GS/s ADC with 1 mW power consumption is designed in 65 nm CMOS based on the proposed architecture. The new architecture is highly scalable with CMOS technology and because of its delay-line-based core, the ADCs performance enhances with further CMOS scaling and provides a promising method for the trend toward more digital implementation of circuits.